Logic Synthesis for Low Power VLSI Designs

By: Sasan Iman, Massoud Pedram

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Hardcover | 30 November 1997

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Hardcover
256 Pages

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24.77 x 16.51 x 2.54

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Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Electronic Devices & Materials Semi-Conductors & Super-Conductors Computing & I.T.Computer Science Computer Architecture & Logic Design Graphical & Digital Media Applications Computer-Aided Design CAD Computer Hardware

Energy Technology & Engineering Electrical Engineering Circuits & Components

Preface
Acknowledgments
Background, Terminology, and Power Modeling	p. 1
Introduction	p. 3
Technology Independent Power Analysis and Modeling	p. 21
Two-level Function Optimization for Low Power	p. 41
Two-Level Logic Minimization in CMOS Circuits	p. 43
Two-Level Logic Minimization in PLAs	p. 69
Multi-level Network Optimization for Low Power	p. 85
Logic Restructuring for Low Power	p. 87
Logic Minimization for Low Power	p. 109
Technology Dependent Optimization for Low Power	p. 149
Post Mapping Structural Optimization for Low Power	p. 183
Power Optimization Methodology	p. 197
POSE: Power Optimization and Synthesis Environment	p. 199
Conclusion	p. 225
Concluding Remarks	p. 227
Index	p. 233
Table of Contents provided by Blackwell. All Rights Reserved.

Logic Synthesis for Low Power VLSI Designs

At a Glance

Hardcover

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