My Wish Lists Login / Join

Logic Synthesis and Verification Algorithms

By: Fabio Somenzi, Gary D. Hachtel

Write A Review

Paperback | 18 March 2013

At a Glance

Paperback
600 Pages

Dimensions(cm)
25.4 x 17.8 x 3.07

Paperback

$139.75

or 4 interest-free payments of $34.94 with

Ships in 5 to 7 business days

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

Shipping

	Standard Shipping	Express Shipping
Metro postcodes:	$9.99	$14.95
Regional postcodes:	$9.99	$14.95
Rural postcodes:	$9.99	$14.95

How to return your order

At Booktopia, we offer hassle-free returns in accordance with our returns policy. If you wish to return an item, please get in touch with Booktopia Customer Care.

Additional postage charges may be applicable.