| Foreword | p. xi |
| Acknowledgments | p. xiii |
| Glossary | p. xv |
| Introduction | p. 1 |
| Legacy Data | p. 5 |
| Modem SOC Flow | p. 5 |
| Legacy Data Review | p. 6 |
| Design Reuse Themes | p. 7 |
| Planned Reuse | p. 7 |
| Unplanned Reuse | p. 8 |
| IP Creation | p. 8 |
| Data Reuse Types and Styles | p. 8 |
| Programmable Cells | p. 9 |
| Fixed Cells | p. 9 |
| Compiled Cells | p. 9 |
| Custom Cells | p. 9 |
| Reasons for Data Migration | p. 11 |
| Functional reuse in derivative products | p. 11 |
| Incorporation of stand alone functions into an SOC | p. 12 |
| Reduced time to market | p. 12 |
| Standardization of design interface | p. 13 |
| Advancement of new manufacturing facility for cost | p. 13 |
| Advancement of a new manufacturing facility by acquisition | p. 14 |
| New Rules for DSM Flows | p. 15 |
| Device Geometries | p. 16 |
| Wafer Type | p. 16 |
| Isolation technique | p. 16 |
| Operating Voltage | p. 17 |
| Process design rules | p. 17 |
| Device performance | p. 17 |
| Interconnect options | p. 18 |
| Memory techniques | p. 19 |
| OPC masking techniques | p. 19 |
| Structured Methodology | p. 21 |
| Assumptions for migration | p. 21 |
| Flowchart of methodology | p. 22 |
| Sequence of the methodology | p. 23 |
| Screening Criteria for Blocks - Step 1 | p. 23 |
| Process Compatibility - Step 2 | p. 23 |
| Test Bench Requirements - Step 3 | p. 23 |
| Block Identification - Step 4 | p. 23 |
| Design Re-Targeting - Step 5 | p. 23 |
| Design Validation - Step 6 | p. 24 |
| Physical Design Migration - Step 7 | p. 25 |
| Post Layout Validation - Step 8 | p. 25 |
| Full Chip Verification - Step 9 | p. 25 |
| Screening Criteria for Blocks | p. 27 |
| Introduction of Case Study | p. 27 |
| Block Selection | p. 28 |
| Description of Selection Criteria | p. 30 |
| Signal Pins | p. 30 |
| Power Supply Pins | p. 31 |
| Input/Output Definitions | p. 31 |
| Performance Definition | p. 34 |
| Hierarchical Application - Schematic | p. 34 |
| Hierarchical Implementation - Layout | p. 37 |
| Layout Application | p. 37 |
| Functional Yield | p. 37 |
| Manufacturing Yield | p. 38 |
| Nominal Test Bench | p. 38 |
| Best/Worst Case Test Bench | p. 39 |
| Process Specific Devices/Parasitic Sensitivity | p. 39 |
| Process Compatibility | p. 41 |
| Process migration tradeoffs | p. 41 |
| Gate material | p. 41 |
| Isolation technique | p. 44 |
| Interconnect scheme | p. 45 |
| Active Device Performance and Models | p. 46 |
| Passive Device Performance and Models | p. 46 |
| Density and Planarization issues | p. 47 |
| Low Density Areas | p. 48 |
| High Density Areas | p. 48 |
| Antenna Requirements | p. 49 |
| Multiple voltage processing | p. 50 |
| Sample USB block tradeoff analysis | p. 52 |
| Gate material | p. 52 |
| Isolation technique | p. 52 |
| Interconnect scheme | p. 52 |
| Active device performance | p. 52 |
| Passive device performance | p. 52 |
| Density and Planarization | p. 53 |
| Antenna Requirements | p. 53 |
| Multiple Voltage Processing | p. 53 |
| Test Bench Requirements | p. 55 |
| Test bench minimum requirements | p. 55 |
| Digital Test Bench | p. 56 |
| Functional Test Bench | p. 56 |
| Timing Test Bench | p. 57 |
| Device Level Test Bench | p. 57 |
| Component Based Test | p. 59 |
| Analog Specialty Function Digital | p. 59 |
| Standard Digital Design Blocks | p. 61 |
| Block Based Test | p. 66 |
| USB Sample Summary | p. 68 |
| Block Identification | p. 69 |
| Physical and Design Views | p. 69 |
| Multiple View Correction | p. 71 |
| Multiple layout implementations | p. 72 |
| Power Supply Pins | p. 72 |
| Multiple Schematic Instance Implementations | p. 74 |
| Hierarchy Tree | p. 75 |
| Test Circuits, Clocks and Power Grids | p. 78 |
| Design Retargeting | p. 79 |
| Device Level Re-Design Stages | p. 80 |
| Nominal Design | p. 80 |
| Corner Based Design | p. 81 |
| Re-Engineering Process - Device Level Design | p. 81 |
| Tool Environment | p. 82 |
| Block Schematic and/or Device Level Netlist | p. 83 |
| Transistor Level Device Models | p. 84 |
| Parametric Constraints for the Block | p. 85 |
| Test Bench for the Block | p. 85 |
| Re-Engineering Process - Corner Based Design | p. 85 |
| Summary for USB Block Migration | p. 89 |
| Design Validation | p. 91 |
| Types of Validation | p. 91 |
| Digital Component Level | p. 92 |
| Analog Component Level | p. 94 |
| Block I/O and Pin Level | p. 97 |
| Block Functional Level | p. 97 |
| Case Study Validation Summary | p. 98 |
| Physical Design Migration | p. 99 |
| Physical Migration Options | p. 99 |
| Design Compaction/Automated Layout Modification | p. 99 |
| Compaction Background | p. 100 |
| Change in Device Topology | p. 102 |
| Addition/Deletion of Device | p. 102 |
| Wiring and Signal Performance Parameters in Addition to DRC Rules | p. 103 |
| Masking Preparation and Problem Avoidance | p. 104 |
| Hierarchical Reconstruction | p. 105 |
| Design Regeneration | p. 106 |
| Device Generation | p. 106 |
| Topology Import | p. 106 |
| Automated Reconstruction | p. 107 |
| Full Custom Design Recreation | p. 107 |
| Case Study Summary | p. 108 |
| Post Layout Validation | p. 111 |
| Design Rule Checking - DRC | p. 111 |
| Layout Vs. Schematic - LVS | p. 114 |
| Power Analysis - IR Drop | p. 115 |
| Noise Analysis and Coupling - Signal Integrity | p. 120 |
| RC Extraction for STA & for Device Simulation | p. 121 |
| Case Study Summary for Physical Verification | p. 122 |
| Full Chip Verification | p. 123 |
| Abstracts Required | p. 123 |
| Logic Design | p. 124 |
| Chip Test Plan | p. 124 |
| Floor Planning | p. 124 |
| Power Budgeting | p. 125 |
| Place and Route | p. 125 |
| Timing Closure | p. 125 |
| Black Box | p. 126 |
| Gray Box | p. 126 |
| Final Verification | p. 126 |
| Bibliography | p. 127 |
| Index | p. 129 |
| Table of Contents provided by Syndetics. All Rights Reserved. |
