Preface ix
1 Digital System Modeling and Simulation 1
1.1 Objectives 1
1.2 Modeling, Synthesis, and Simulation Design 1
1.3 History of Digital Systems 2
1.4 Standard Logic Devices 2
1.5 Custom-Designed Logic Devices 3
1.6 Programmable Logic Devices 3
1.7 Simple Programmable Logic Devices 4
1.8 Complex Programmable Logic Devices 5
1.9 Field-Programmable Gate Arrays 6
1.10 Future of Digital Systems 7
Problems 8
2 Number Systems 9
2.1 Objectives 9
2.2 Bases and Number Systems 9
2.3 Number Conversions 11
2.4 Data Organization 13
2.5 Signed and Unsigned Numbers 13
2.6 Binary Arithmetic 16
2.7 Addition of Signed Numbers 17
2.8 Binary-Coded Decimal Representation 19
2.9 BCD Addition 20
Problems 21
3 Boolean Algebra and Logic 24
3.1 Objectives 24
3.2 Boolean Theory 24
3.3 Logic Variables and Logic Functions 25
3.4 Boolean Axioms and Theorems 25
3.5 Basic Logic Gates and Truth Tables 27
3.6 Logic Representations and Circuit Design 27
3.7 Truth Table 28
3.8 Timing Diagram 31
3.9 Logic Design Concepts 31
3.10 Sum-of-Products Design 32
3.11 Product-of-Sums Design 33
3.12 Design Examples 34
3.13 NAND and NOR Equivalent Circuit Design 36
3.14 Standard Logic Integrated Circuits 37
Problems 39
4 VHDL Design Concepts 46
4.1 Objectives 46
4.2 CAD Toolâ"Based Logic Design 46
4.3 Hardware Description Languages 47
4.4 VHDL Language 48
4.5 VHDL Programming Structure 48
4.6 Assignment Statements 51
4.7 VHDL Data Types 51
4.8 VHDL Operators 55
4.9 VHDL Signal and Generate Statements 56
4.10 Sequential Statements 58
4.11 Loops and Decision-Making Statements 59
4.12 Subcircuit Design 61
4.13 Packages and Components 61
Problems 64
5 Integrated Logic 68
5.1 Objectives 68
5.2 Logic Signals 68
5.3 Logic Switches 69
5.4 NMOS and PMOS Logic Gates 70
5.5 CMOS Logic Gates 72
5.6 CMOS Logic Networks 75
5.7 Practical Aspects of Logic Gates 76
5.8 Transmission Gates 79
Problems 81
6 Logic Function Optimization 87
6.1 Objectives 87
6.2 Logic Function Optimization Process 87
6.3 Karnaugh Maps 87
6.4 Two-Variable Karnaugh Map 89
6.5 Three-Variable Karnaugh Map 90
6.6 Four-Variable Karnaugh Map 91
6.7 Five-Variable Karnaugh Map 93
6.8 XOR and NXOR Karnaugh Maps 94
6.9 Incomplete Logic Functions 94
6.10 Quineâ"McCluskey Minimization 96
Problems 99
7 Combinational Logic 105
7.1 Objectives 105
7.2 Combinational Logic Circuits 105
7.3 Multiplexers 106
7.4 Logic Design with Multiplexers 111
7.5 Demultiplexers 112
7.6 Decoders 113
7.7 Encoders 115
7.8 Code Converters 116
7.9 Arithmetic Circuits 120
Problems 129
8 Sequential Logic 133
8.1 Objectives 133
8.2 Sequential Logic Circuits 133
8.3 Latches 134
8.4 Flip-Flops 138
8.5 Registers 145
8.6 Counters 149
Problems 158
9 Synchronous Sequential Logic 165
9.1 Objectives 165
9.2 Synchronous Sequential Circuits 165
9.3 Finite-State Machine Design Concepts 167
9.4 Finite-State Machine Synthesis 171
9.5 State Assignment 178
9.6 One-Hot Encoding Method 180
9.7 Finite-State Machine Analysis 182
9.8 Sequential Serial Adder 184
9.9 Sequential Circuit Counters 188
9.10 State Optimization 195
9.11 Asynchronous Sequential Circuits 199
Problems 201
Index 213
