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Interconnect Technology and Design for Gigascale Integration - Jeffrey A. Davis

Interconnect Technology and Design for Gigascale Integration

By: Jeffrey A. Davis (Editor), James D. Meindl (Editor)

Hardcover Published: 31st October 2003
ISBN: 9781402076060
Number Of Pages: 411

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The International Technology Roadmap for Semiconductors (ITRS) projects that by 2011 over one billion transistors will be integrated into a single monolithic die. The wiring system of this billion-transistor die will deliver power to each transistor, provide a low-skew synchronizing clock to latches and dynamic circuits, and distribute data and control signals throughout the chip. The resulting design and modeling complexity of this GSI multilevel interconnect network is enormous such that over one hundred quadrillion coupling inductances and capacitances throughout a nine-to-ten-level metal stack must be managed. Interconnect Technology and Design for Gigascale Integration will address the limits and opportunities for GSI interconnect design and technology in the twenty-first century.
Interconnect Technology and Design for Gigascale Integration is the cumulative effort from academic researchers at Georgia Tech, MIT, and Stanford, as well as from industry researchers at IBM T.J. Watson Research Center, LSI Logic, and SUN microsystems. The material found in this book is unique in that it spans IC interconnect topics ranging from IBM's revolutionary copper process to an in depth exploration into interconnect-aware computer architectures. This broad swath of topics presented by leaders in the research field is intended to provide a comprehensive perspective on interconnect technology and design issues so that the reader will understand the implications of the semiconductor industry's next substantial milestone - gigascale integration.

Interconnect Opportunities for GSIp. 1
Copper BEOL Interconnects for Silicon CMOS Logic Technologyp. 35
Interconnect Parasitic Extraction of Resistance, Capacitance, and Inductancep. 67
Distributed RC and RLC Transient Modelsp. 111
Power, Clock, and Global Signal Distributionp. 159
Stochastic Multilevel Interconnect Modeling and Optimizationp. 219
Interconnect-Centric Computer Architecturesp. 263
Chip-to-Module Interconnectp. 293
3-D ICs DSM Interconnect Performance Modeling and Analysisp. 323
Silicon Microphotonicsp. 383
Table of Contents provided by Blackwell. All Rights Reserved.

ISBN: 9781402076060
ISBN-10: 1402076061
Audience: General
Format: Hardcover
Language: English
Number Of Pages: 411
Published: 31st October 2003
Publisher: Springer-Verlag New York Inc.
Country of Publication: US
Dimensions (cm): 24.64 x 16.1  x 2.79
Weight (kg): 0.84

Earn 519 Qantas Points
on this Book