Interconnect Technology and Design for Gigascale Integration

By: Jeffrey A. Davis (Editor), James D. Meindl (Editor)

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Hardcover | 31 October 2003

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432 Pages

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23.5 x 15.88 x 2.54

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The International Technology Roadmap for Semiconductors (ITRS) projects that by 2011 over one billion transistors will be integrated into a single monolithic die. The wiring system of this billion-transistor die will deliver power to each transistor, provide a low-skew synchronizing clock to latches and dynamic circuits, and distribute data and control signals throughout the chip. The resulting design and modelling complexity of this GSI multilevel interconnect network is enormous such that over one hundred quadrillion coupling inductances and capacitances throughout a nine-to-ten-level metal stack must be managed. "Interconnect Technology and Design for Gigascale Integration" addresses the limits and opportunities for GSI interconnect design and technology in the 21st century. The text is the cumulative effort from academic researchers at Georgia Tech, MIT, and Stanford, as well as from industry researchers at IBM T.J. Watson Research Center, LSI Logic, and SUN microsystems. The material found in this book is unique in that it spans IC interconnect topics ranging from IBM's revolutionary copper process to an in depth exploration into interconnect-aware computer architectures. This broad swath of topics presented by leaders in the research field is intended to provide a comprehensive perspective on interconnect technology and design issues so that the reader will understand the implications of the semiconductor industry's next substantial milestone - gigascale integration.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Electronic Devices & Materials Semi-Conductors & Super-Conductors Energy Technology & Engineering Electrical Engineering

Preface
Interconnect Opportunities for GSI	p. 1
Copper BEOL Interconnects for Silicon CMOS Logic Technology	p. 35
Interconnect Parasitic Extraction of Resistance, Capacitance, and Inductance	p. 67
Distributed RC and RLC Transient Models	p. 111
Power, Clock, and Global Signal Distribution	p. 159
Stochastic Multilevel Interconnect Modeling and Optimization	p. 219
Interconnect-Centric Computer Architectures	p. 263
Chip-to-Module Interconnect	p. 293
3-D ICs DSM Interconnect Performance Modeling and Analysis	p. 323
Silicon Microphotonics	p. 383
Table of Contents provided by Blackwell. All Rights Reserved.

Interconnect Technology and Design for Gigascale Integration

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