Integrated System-Level Modeling of Network-On-Chip Enabled Multi-Processor Platforms

By: Tim Kogel, Rainer Leupers, Heinrich Meyr

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Hardcover | 5 July 2006

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216 Pages

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24.13 x 15.24 x 0.64

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We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore's law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.

Industry Reviews

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"The book covers most of the major areas of system-level design and modeling, and much of the work described has been incorporated into a commercial ESL tool ... . This book's scope and range of pragmatic ideas make it valuable for a wide audience. ... When combined with the extensive list of references (260!), this is a very valuable resource for anyone interested in the area ... . It should resonate with students, researchers, and practical designers ... ." (Grant Martin, IEEE Design and Test of Computers, May-June, 2007)

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Paperback

Published: 19th November 2010

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Introduction	p. 1
Embedded SoC applications	p. 9
Classification of platform elements	p. 15
System level design principles	p. 33
Related work	p. 43
Methodology overview	p. 59
Unified timing model	p. 79
MP-SoC simulation framework	p. 113
Case study	p. 141
Summary	p. 153
The OSCI TLM standard	p. 159
The OCPIP TL3 channel	p. 163
The architects view framework	p. 167
Table of Contents provided by Blackwell. All Rights Reserved.

Integrated System-Level Modeling of Network-On-Chip Enabled Multi-Processor Platforms

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Industry Reviews

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