Integrated Circuit Test Engineering

Modern Techniques

By: Ian A. Grout

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Paperback | 22 August 2005

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396 Pages

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22.86 x 15.24 x 1.91

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Taking a three-pronged approach - test engineering from traditional-test, design and manufacturing view-points - Integrated Circuit Test Engineering encapsulates the subject as it stands today. After introductory background from basic testing rules to trends in technology, the reader learns about: fabrication processes; a complete range of detailed tests and procedures; how to design for testability; fault simulation; automatic test equipment and the economics of testing. The text incudes: Worked examples and exercises, well-organized references and bibliography. - An introduction to the use of various software and languages such as MATLAB, Spice, Verilog-HDL and VHDL. - A series of experiments based on material downloaded from springeronline.com showing how to construct a hardware test arrangement for MS Windows PCs. This book is a practical tool for advanced undergraduate and graduate electronic engineering students, a resource for their tutors and a guide for the practising electronic engineer.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Technology in General Engineering in General Energy Technology & Engineering Electrical Engineering Computing & I.T.Computer Hardware Personal Computers

Computer Science Systems Analysis & Design Mechanical Engineering & Materials Production & Industrial Engineering

Abbreviations	p. xxv
Introduction to Integrated Circuit Test Engineering	p. 1
Introduction	p. 1
The Rule of Ten	p. 3
The Evolution of Test Engineering	p. 3
Test Engineer Activities	p. 4
Device Testing	p. 7
Production Test: ATE Systems	p. 8
Technology Trends	p. 10
International Technology Roadmap for Semiconductors (ITRS)	p. 11
Computer Aided Test	p. 12
Virtual Test	p. 12
Moore's Law	p. 12
Rent's Rule	p. 13
Benchmark Circuits	p. 14
DfX	p. 14
Summary	p. 14
References	p. 15
Fabrication Processes for Integrated Circuits	p. 17
Introduction	p. 17
Technology Nodes	p. 19
Wafer Size	p. 20
Bipolar Technology	p. 21
Complementary Metal Oxide Semiconductor (CMOS) Technology	p. 22
BiCMOS Technology	p. 29
SiGe BiCMOS Technology	p. 29
Gallium Arsenide (GaAs) Technology	p. 29
Memory Processes	p. 29
Packaging	p. 30
Die Bonding	p. 31
Multi-Chip Modules	p. 32
Foundry Services	p. 34
Process Variations	p. 35
Electromigration	p. 35
Future Directions	p. 35
Summary	p. 36
References	p. 37
Exercises	p. 38
Digital Logic Test	p. 41
Introduction	p. 41
Logic Families	p. 44
Digital Logic ICs	p. 45
Programmable Logic	p. 46
Basic Logic Gates	p. 48
Hardware Description Languages	p. 49
Digital Circuit and System Design Flow	p. 50
Number Systems	p. 52
CMOS Inverter	p. 53
Latch-Up	p. 61
Introduction to Digital Logic Test	p. 62
Fault Models	p. 66
Stuck-At-Fault	p. 66
Bridging Fault	p. 67
Delay Fault	p. 69
Memory Fault	p. 69
Stuck-Open and Stuck Short Faults	p. 70
I[subscript DDQ] Fault	p. 70
Combinational Logic Test	p. 74
Introduction	p. 74
Test Pattern Generation	p. 74
Non-Detectable Faults Due to Circuit Redundancy	p. 75
Fan-out and Reconvergence	p. 76
Local and Global Feedback	p. 77
Multiple Faults and Fault Masking	p. 77
Limitations of Fault Models	p. 77
The Fault Matrix	p. 77
Sequential Logic Test	p. 81
Introduction	p. 81
D-Type Bistable	p. 82
Example Circuits	p. 83
DfT and BIST Overview	p. 85
Future Directions	p. 86
Summary	p. 88
References	p. 88
Exercises	p. 91
Memory Test	p. 95
Introduction	p. 95
Memory Overview	p. 95
Read Only Memory (ROM)	p. 98
Random Access Memory (RAM)	p. 98
SRAM Structure	p. 99
DRAM Structure	p. 102
ROM structure	p. 104
Fault Modelling in Memory	p. 105
RAM Test Algorithms	p. 107
Introduction	p. 107
Notation	p. 108
RAM Test Algorithms	p. 109
Memory Access for Test	p. 112
Memory BIST	p. 113
ROM Test	p. 115
Future Directions	p. 115
Summary	p. 117
References	p. 117
Exercises	p. 119
Analogue Test	p. 123
Introduction	p. 123
Analogue Circuit Overview	p. 126
Measuring Analogue Parameters	p. 130
Coherent Sampling	p. 133
Functional vs Structural Test	p. 136
Fault Modelling in Analogue	p. 136
Future Directions	p. 137
Summary	p. 138
References	p. 139
Exercises	p. 141
Mixed-Signal Test	p. 143
Introduction	p. 143
Mixed-Signal Circuit Test Overview	p. 145
Fault Modelling in Mixed-Signal Circuits	p. 147
DAC Architectures	p. 148
Introduction	p. 148
Binary-Weighted Resistor DAC	p. 151
Binary-Weighted Current DAC	p. 152
R-2R Ladder DAC	p. 152
Resistor String DAC	p. 153
Segmented Resistor String DAC	p. 153
Sigma-Delta ([Sigma Delta]) DAC	p. 154
Hybrid DAC	p. 154
DAC Test	p. 155
Introduction	p. 155
Static (DC) Tests	p. 155
Transfer Curve Tests	p. 156
Dynamic Tests	p. 158
FFT, SNR, SFDR and THD	p. 159
ADC Architectures	p. 159
Introduction	p. 159
Successive Approximation ADC	p. 161
Integrating (Single and Dual Slope) ADC	p. 162
Flash ADC	p. 162
Sigma-Delta ([Sigma Delta]) ADC	p. 163
ADC test	p. 163
Introduction	p. 163
Static (DC) and Transfer Curve Tests	p. 164
Dynamic Tests	p. 166
FFT Test	p. 166
Code Density (Histogram) Test	p. 166
Future Directions	p. 168
Summary	p. 169
References	p. 169
Exercises	p. 171
Input-Output Test	p. 175
Introduction	p. 175
Electrical Overstress and Electrostatic Discharge	p. 178
Digital I/O Structures	p. 179
Introduction	p. 179
CMOS Inverter	p. 182
Logic Design Variants	p. 186
TTL Family Variants	p. 186
CMOS Family Variants	p. 187
Digital Cell Schematics	p. 188
Digital I/O Test	p. 188
Introduction	p. 188
Measuring Input Cell Voltage and Current	p. 191
Measuring Output Cell Voltage and Current	p. 191
Dealing with Bidirectional Cells	p. 192
Dealing with Internal Pull-Ups and Pull-Downs	p. 192
Analogue I/O Structures	p. 192
Analogue I/O Test	p. 193
Future Directions	p. 193
Summary	p. 194
References	p. 195
Design for Testability - Structured Test Approaches	p. 197
Introduction	p. 197
Observability and Controllability	p. 198
Digital DfT	p. 199
Design Partitioning	p. 199
Scan Path Test	p. 200
Built-In Self-Test (BIST)	p. 204
1149.1 Boundary Scan	p. 208
P1500 Core Test Standard Development	p. 212
Analogue and Mixed-Signal DfT	p. 212
Overview	p. 212
1149.4 Mixed-Signal Test Bus	p. 215
Future Directions for DfT and BIST	p. 217
Summary	p. 218
References	p. 218
Exercises	p. 221
System on a Chip (SoC) Test	p. 225
Introduction	p. 225
Examples of SoC Devices	p. 228
Test Complexity and Additional Problems	p. 228
P1500 Core Test Standard Development	p. 229
Future Directions for SoC Test	p. 230
Summary	p. 231
References	p. 232
Test Pattern Generation and Fault Simulation	p. 235
Introduction	p. 235
Test Pattern Generation	p. 238
Digital Fault Simulation	p. 240
Analogue Fault Simulation	p. 243
Mixed-Signal Fault Simulation	p. 247
Issues with Fault Simulation	p. 248
Circuit vs Behavioural Level Fault Simulation	p. 249
Future Directions	p. 249
Summary	p. 250
References	p. 250
Exercises	p. 253
Automatic Test Equipment (ATE) and Production Test	p. 257
Introduction	p. 257
Production Test Flow	p. 258
ATE Systems	p. 260
Future Directions for ATE Systems	p. 264
Summary	p. 265
References	p. 265
Test Economics	p. 267
Introduction	p. 267
Purpose of a Test Economics Model	p. 269
Test Economics Model Development	p. 271
Summary	p. 273
References	p. 274
Appendices
Introduction to VHDL	p. 275
Introduction	p. 275
Entities and Architectures	p. 276
Libraries, Packages and Configurations	p. 277
VHDL Testbench	p. 277
References	p. 278
Introduction to Verilgo -HDL	p. 279
Introduction	p. 279
Verilog -HDL Modules	p. 280
Verilog -HDL Testfixture	p. 280
Data Types	p. 280
Lexical Conventions	p. 281
Example	p. 282
References	p. 284
Introduction to Spice	p. 285
Introduction	p. 285
Scope of Discussions	p. 286
Input File Format	p. 286
Commenting the Input File	p. 287
Analyses	p. 288
Input Stimuli	p. 288
Defining Components in Spice	p. 289
Scale Factors in Spice	p. 289
Dealing with Design Hierarchy	p. 290
References	p. 290
Introduction to MATLAB	p. 291
Introduction	p. 291
Interactive and Batch Modes	p. 292
Scalar Variables and Arithmetic Operators	p. 293
Useful Commands	p. 293
Matrix Variables and Arithmetic Operators	p. 294
Signals and Results Plotting	p. 294
References	p. 296
Hardware Experimentation	p. 297
Introduction	p. 297
Generic Tester Arrangement	p. 298
CPLD Based Logic and Memory Tester	p. 300
References	p. 302
VHDL Simulation Examples	p. 303
Introduction	p. 303
2-Input Combinational Logic Circuit	p. 305
8-Input Priority Encoder	p. 308
3-Bit Binary Counter	p. 311
3-Bit Linear Feedback Shift Register (LFSR)	p. 314
Simple 4 x 8-Bit ROM	p. 316
Simple 4 x 8-Bit RAM	p. 319
HSPICE Simulation Examples	p. 323
Introduction	p. 323
Series Resonant LCR Circuit	p. 324
MOS Transistor Amplifier	p. 325
CMOS Inverter	p. 326
3-Bit DAC	p. 327
MATLAB Simulation Examples	p. 331
Introduction	p. 331
DAC example	p. 332
ADC example	p. 335
Journals, Conferences and Organisations	p. 341
Bibliography	p. 345
Index	p. 359
Table of Contents provided by Ingram. All Rights Reserved.

Integrated Circuit Test Engineering

Modern Techniques

At a Glance

Paperback

Shipping

How to return your order

Defective items

You Can Find This Book In

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