High Performance Memory Testing

Design Principles, Fault Modeling and Self-Test

By: R. Dean Adams

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Hardcover | 30 September 2002

At a Glance

Hardcover
268 Pages

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23.39 x 15.6 x 1.6

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Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully.
High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test.

High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.

Industry Reviews

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"Fulfilling a need in the industry and a need in the literature, the book is certain to stimulate a heightened research interest in memory test, memory design, and memory elf test, each of which by itself constitutes an intriguing subject. The observations and approaches of the book make it a most useful work for the professional and the researcher in helping them understand the memories that are being tested." (Current Engineering Practice, Vol. 47, 2002-2003)

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Paperback

Published: 26th April 2013

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Preface	p. vii
Design & Test of Memories
Opening Pandora's Box	p. 1
What is a Memory, Test, BIST?	p. 2
The Ubiquitous Nature of Memories	p. 3
The Complexity of Memories	p. 4
It was the best of memories, it was the worst of memories...	p. 8
Testing: Bits is Not Bits	p. 9
Best BIST or Bust: The journey toward the best self test	p. 11
Ignorance is Not Bliss	p. 13
Conclusions	p. 14
Static Random Access Memories	p. 17
SRAM Trends	p. 18
The Cell	p. 20
Read Data Path	p. 25
Write Driver Circuit	p. 37
Decoder Circuitry	p. 38
Layout Considerations	p. 40
Redundancy	p. 44
Summary	p. 46
Multi-Port Memories	p. 47
Cell Basics	p. 48
Multi-Port Memory Timing Issues	p. 53
Layout Considerations	p. 54
Summary	p. 56
Silicon On Insulator Memories	p. 57
Silicon On Insulator Technology	p. 57
Memories in SOI	p. 60
Layout Considerations	p. 64
Summary	p. 66
Content Addressable Memories	p. 67
CAM Topology	p. 68
Masking	p. 71
CAM Features	p. 74
Summary	p. 75
Dynamic Random Access Memories	p. 77
DRAM Trends	p. 78
The DRAM cell	p. 79
The DRAM Capacitor	p. 81
DRAM Cell Layout	p. 83
DRAM Operation	p. 84
Conclusions	p. 88
Non-Volatile Memories	p. 89
ROM	p. 89
EEPROM & Flash	p. 90
The Future of memories	p. 95
FeRAM	p. 96
MRAM	p. 98
Ovonic	p. 99
And Beyond	p. 100
Conclusions	p. 101
Memory Testing
Memory Faults	p. 103
A Toast: To Good Memories	p. 103
Fault Modeling	p. 104
General Fault modeling	p. 108
Read Disturb Fault Model	p. 112
Pre-charge Faults	p. 114
False Write Through	p. 115
Data Retention Faults	p. 116
SOI Faults	p. 118
Decoder Faults	p. 119
Multi-port Memory Faults	p. 121
Other Fault Models	p. 125
Memory Patterns	p. 127
Zero-One Pattern	p. 128
Exhaustive Test Pattern	p. 129
Walking, Marching, and Galloping	p. 130
Bit and Word Orientation	p. 132
Common Array Patterns	p. 133
Common March Patterns	p. 136
March C- Pattern	p. 136
Partial Moving Inversion Pattern	p. 137
Enhanced March C- Pattern	p. 138
March LR Pattern	p. 139
March G Pattern	p. 139
SMarch Pattern	p. 140
Pseudo-Random Patterns	p. 141
CAM Patterns	p. 142
SOI Patterns	p. 145
Multi-Port Memory Patterns	p. 145
Summary	p. 148
Memory Self Test
BIST Concepts	p. 149
The Memory Boundary	p. 150
Manufacturing Test and Beyond	p. 152
ATE and BIST	p. 153
At-Speed Testing	p. 154
Deterministic BIST	p. 154
Pseudo-Random BIST	p. 155
Conclusions	p. 162
State Machine BIST	p. 163
Counters and BIST	p. 164
A Simple Counter	p. 164
Read/Write Generation	p. 166
The BIST Portions	p. 169
Programming and State Machine BISTs	p. 171
Complex Patterns	p. 171
Conclusions	p. 172
Micro-Code BIST	p. 173
Micro-code BIST Structure	p. 173
Micro-code Instructions	p. 175
Looping and Branching	p. 177
Using a Micro-coded Memory BIST	p. 179
Conclusions	p. 181
BIST and Redundancy	p. 183
Replace, Not Repair	p. 184
Redundancy Types	p. 184
Hard and Soft Redundancy	p. 187
Challenges in BIST and Redundancy	p. 188
The Redundancy Calculation	p. 190
Conclusions	p. 193
Design For Test and BIST	p. 195
Weak Write Test Mode	p. 196
Bit Line Contact Resistance	p. 197
PFET Test	p. 199
Shadow Write and Shadow Read	p. 200
General Memory DFT Techniques	p. 201
Conclusions	p. 202
Conclusions	p. 203
The Right BIST for the Right Design	p. 203
Memory Testing	p. 204
The Future of Memory Testing	p. 206
Appendices
Further Memory Fault Modeling	p. 207
Linked Faults	p. 207
Coupling Fault Models	p. 208
Inversion Coupling Fault	p. 208
Idempotent Coupling Fault	p. 208
Complex Coupling Fault	p. 209
State Coupling Fault	p. 209
V Coupling Fault	p. 209
Neighborhood Pattern Sensitive Fault Models Expanded	p. 210
Pattern Sensitive Fault Model	p. 210
Active Neighborhood Pattern Sensitive Fault Model	p. 210
Passive Neighborhood Pattern Sensitive Fault Model	p. 210
Static Neighborhood Pattern Sensitive Fault Model	p. 210
Recovery Fault Models	p. 210
Sense Amplifier Recovery Fault Model	p. 210
Write Recovery Fault Model	p. 211
Slow write Recovery Fault Model	p. 211
Stuck Open Fault Models	p. 211
Stuck Open Cell Fault Model	p. 211
Stuck Open Bit Line Fault Model	p. 211
Imbalanced Bit Line Fault Model	p. 211
Multi-Port Memory Faults	p. 212
Further Memory Test Patterns	p. 213
MATS Patterns	p. 213
MATS	p. 213
MATS+	p. 214
MATS++	p. 214
Marching 1/0	p. 214
Lettered March Patterns	p. 215
March A	p. 215
March B	p. 215
March C	p. 215
March X	p. 216
March Y	p. 216
March C+, C++, A+, A++ Patterns	p. 216
March LA	p. 217
March SR+	p. 217
IFA Patterns	p. 218
9N Linear	p. 218
13N	p. 218
Other Patterns	p. 219
MovC	p. 219
Moving Inversion	p. 219
Butterfly	p. 220
SMARCH	p. 220
Pseudo-Random	p. 221
State Machine HDL	p. 223
References	p. 229
Glossary / Acronyms	p. 241
Index	p. 243
About the Author	p. 247
Table of Contents provided by Ingram. All Rights Reserved.

High Performance Memory Testing

Design Principles, Fault Modeling and Self-Test

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