High Performance Design Automation for Multi-Chip Modules

By: Jun Dong Cho (Editor), Paul D Franzon (Editor)

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Hardcover | 1 December 1995

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Hardcover
264 Pages

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26.04 x 17.78 x 1.91

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Today's electronics industry requires new design automation methodologies that allow designers to incorporate high performance integrated circuits into smaller packaging. The aim of this book is to provide current and future techniques and algorithms of high performance multichip modules and other packaging methodologies. Technical papers in this issue cover: design optimization and physical partitioning; global routing/multi-layer assignment; timing-driven interconnection design (timing models, clock and power design); crosstalk, reflection, and simultaneous switching noise minimization; yield optimization; defect area minimization; low-power physical layout; design methodologies. Two tutorial reviews review some of the most significant algorithms previously developed for the placement/partitioning, and signal integrity issues, respectively. The remaining articles review the trend of prime design automation algorithms to solve the above eight problems arisen in MCM and other packages.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Technology in General Engineering in General Computing & I.T.Computer Science Booktopia Publisher Services World Scientific Publishing Energy Technology & Engineering

Electrical Engineering

Preface
An Overview of Placement and Routing Algorithms for Multi-Chip Modules	p. 3
Early Feasability and Cost Assessment for Multichip Module Technologies	p. 25
Pin Redistribution Problem for Multi-Chip Modules: Algorithms and Complexity	p. 43
Layer Assignment for High-Speed MCM Packaging	p. 61
63-Layer TCM Wiring with Three-Dimensional Crosstalk Constraints	p. 81
A New Layout Design System for Multichip Modules	p. 93
An Overview of Techniques for Partitioning Multichip Modules	p. 125
Interconnect Design and Synthesis in High Speed Printed Circuit Boards and Multi-Chip Modules	p. 141
Board Level Partitioning for Improved Partial Scan	p. 159
Optimal Algorithms for Substrate Testing in Multi-Chip Modules	p. 181
Three-Dimensional Packaging for High-Performance Interconnect in Large-Scale VLSI Systems	p. 199
Area Efficient Layout of Balanced Hypercubes	p. 217
Simultaneous Switching Noise Analysis of a 16 Mb x 9 DRAM SIMM Memory Module	p. 233
Table of Contents provided by Blackwell. All Rights Reserved.

High Performance Design Automation for Multi-Chip Modules

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