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FPGA Design

Best Practices for Team-Based Design

By: Philip Simpson

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Hardcover | 11 August 2010

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Hardcover
168 Pages

Dimensions(cm)
24.4 x 16.6 x 1.6

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Published: 30th June 2015

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In August of 2006, an engineering VP from one of Altera's customers approached Misha Burich, VP of Engineering at Altera, asking for help in reliably being able to predict the cost, schedule and quality of system designs reliant on FPGA designs. At this time, I was responsible for defining the design flow requirements for the Altera design software and was tasked with investigating this further. As I worked with the customer to understand what worked and what did not work reliably in their FPGA design process, I noted that this problem was not unique to this one customer. The characteristics of the problem are shared by many Corporations that implement designs in FPGAs. The Corporation has many design teams at different locations and the success of the FPGA projects vary between the teams. There is a wide range of design experience across the teams. There is no working process for sharing design blocks between engineering teams. As I analyzed the data that I had received from hundreds of customer visits in the past, I noticed that design reuse among engineering teams was a challenge. I also noticed that many of the design teams at the same Companies and even within the same design team used different design methodologies. Altera had recently solved this problem as part of its own FPGA design software and IP development process.

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Non-Fiction Computing & I.T.Computer Science Computer Architecture & Logic Design Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Graphical & Digital Media Applications Computer-Aided Design CAD Business & Management Management & Management Techniques

Project Management

Best Practices for Successful FPGA Design	p. 1
Introduction	p. 1
Project Management	p. 5
The Role of Project Management	p. 5
Project Management Phases	p. 5
Estimating a Project Duration	p. 6
Schedule	p. 6
Design Specification	p. 9
Design Specification: Communication Is Key to Success	p. 9
High Level Functional Specification	p. 9
Functional Design Specification	p. 10
Resource Scoping	p. 15
Introduction	p. 15
Engineering Resources	p. 15
Third Party IP	p. 16
Device Selection	p. 16
Silicon Specially Features	p. 17
Density	p. 18
Speed Requirements	p. 19
Pin-Out	p. 19
Power	p. 20
Availability of IP	p. 20
Availability of Silicon	p. 20
Summary	p. 21
Design Environment	p. 23
Introduction	p. 23
Scripting Environment	p. 23
Interaction with Version Control Software	p. 24
Use of a Problem Tracking System	p. 25
A Regression Test System	p. 26
When to Upgrade the Versions of the FPGA Design Tools	p. 26
Common Tools in the FPGA Design Environment	p. 27
Board Design	p. 29
Challenges that FPGAs Create for Board Design	p. 29
Engineering Roles and Responsibilities	p. 30
FPGA Engineers	p. 30
PCB Design Engineer	p. 31
Signal Integrity Engineer	p. 32
Power and Thermal Considerations	p. 33
Filtering Power Supply Noise	p. 33
Power Distribution	p. 33
Signal Integrity	p. 34
Types of Signal Integrity Problems	p. 34
Electromagnetic Interference	p. 35
Design Flows for Creating the FPGA Pinout	p. 36
User Flow 1: FPGA Designer Driven	p. 36
User Flow 2	p. 38
How Do FPGA and Board Engineers Communicate Pin Changes?	p. 40
Board Design Check List for a Successful FPGA Pin-Out	p. 40
Power and Thermal Analysis	p. 41
Introduction	p. 41
Power Basics	p. 42
Static Power	p. 42
Dynamic Power	p. 42
I/O power	p. 42
Inrush Current	p. 43
Configuration Power	p. 43
Key Factors in Accurate Power Estimation	p. 43
Accurate Power Models of the FPGA Circuitry	p. 44
Accurate Toggle Rate Data on Each Signal	p. 44
Accurate Operating Conditions	p. 45
Resource Utilization	p. 46
Power Estimation Early in the Design Cycle (Power Supply Planning)	p. 46
Simulation Based Power Estimation (Design Power Verification)	p. 47
Partial Simulations	p. 50
Best Practices for Power Estimation	p. 50
RTL Design	p. 51
Introduction	p. 51
Common Terms and Terminology	p. 51
Recommendations for Engineers with an ASIC Design Background	p. 53
Recommended FPGA Design Guidelines	p. 54
Synchronous Versus Asynchronous	p. 54
Global Signals	p. 54
Dedicated Hardware Blocks	p. 55
Use of Low-Level Design Primitives	p. 56
Managing Metastability	p. 57
Writing Effective HDL	p. 57
What's the Best Language	p. 58
Good Design Practices	p. 59
HDL for Synthesis	p. 65
Analyzing the RTL Design	p. 75
Synthesis Reports	p. 75
Messages	p. 76
Block Diagram View	p. 77
Recommended Best Practices for RTL Design	p. 78
IP and Design Reuse	p. 79
Introduction	p. 79
The Need for IP Reuse	p. 79
Benefits of IP Reuse	p. 80
Challenges in Developing a Design Reuse Methodology	p. 80
Make Versus Buy	p. 82
Architecting Reusable IP	p. 83
Specification	p. 83
Implementation Methods	p. 83
Use of Standard Interfaces	p. 85
Packaging of IP	p. 86
Documentation	p. 87
User Interface	p. 87
Compatibility with System Integration Tools	p. 88
IP Security	p. 89
IP Reuse Checklist	p. 90
The Hardware to Software Interface	p. 91
Software Interface	p. 91
Definition of Register Address Map	p. 91
Use of the Register Address Map	p. 91
IP Selection	p. 92
Software Engineers Interface	p. 92
RTL Engineers Interface	p. 92
Verification Interface	p. 93
Documentation	p. 93
Summary	p. 94
Functional Verification	p. 95
Introduction	p. 95
Challenges of Functional Verification	p. 95
Glossary of Verification Concepts	p. 96
RTL Versus Gate Level Simulation	p. 97
Verification Methodology	p. 97
Attack Complexity	p. 98
Modularize Your Design and Your Tests	p. 98
Plan for Expected Operation	p. 98
Plan for the Unexpected	p. 98
Functional Coverage	p. 99
Directed Testing	p. 100
Random Dynamic Simulation	p. 100
Constrained Random Tests	p. 100
Use of System Verilog for Design and Verification	p. 100
General Testbench Methods	p. 101
Self Verifying Testbenches	p. 102
Formal Equivalency Checking	p. 103
Code Coverage	p. 104
QA Testing	p. 104
Functional Regression Testing	p. 104
GUI Testing for Reusable IP	p. 105
Hardware Interoperability Tests	p. 105
Hardware/Software Co-Verification	p. 106
Getting to Silicon Fast	p. 106
Functional Verification Checklist	p. 106
Timing Closure	p. 107
Timing Closure Challenges	p. 107
The Importance of Timing Assignments and Timing Analysis	p. 108
Background	p. 108
Basics of Timing Analysis	p. 109
A Methodology for Successful Timing Closure	p. 115
Family and Device Assignments	p. 115
Design Planning	p. 116
Early Timing Estimation	p. 121
CAD Tool Settings	p. 122
Common Timing Closure Issues	p. 129
Missing Timing Constraints	p. 130
Conflicting Timing Constraints	p. 130
High Fan-Out Registers	p. 130
Missing Timing by a Small Margin	p. 131
Restrictive Location Constraints	p. 131
Long Compile Times	p. 131
Design Planning, Implementation, Optimization and Timing Closure Checklist	p. 132
In-System Debug	p. 133
In-System Debug Challenges	p. 133
Planning	p. 134
Techniques	p. 134
Use of Pins for Debug	p. 134
Internal Logic Analyzer	p. 135
Use of Debug Logic	p. 138
External Logic Analyzer	p. 139
Editing Memory Contents	p. 139
Use of a Soft Processor for Debug	p. 140
Use Scenarios	p. 140
Power-Up Debug	p. 140
Debug of Transceiver Interfaces	p. 141
Reporting of System Performance	p. 141
Debug of Soft Processors	p. 142
Device Programming Issues	p. 143
In-System Debug Checklist	p. 144
Design Sign-Off	p. 145
Sign-Off Process	p. 145
After Sign-Off	p. 145
Bibliography	p. 147
Index	p. 149
Table of Contents provided by Ingram. All Rights Reserved.

FPGA Design

Best Practices for Team-Based Design

At a Glance

New Edition

Hardcover

Shipping

How to return your order

Defective items

You Can Find This Book In

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