Formal Semantics and Proof Techniques for Optimizing VHDL Models

By: Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey

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Hardcover | 30 November 1998

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184 Pages

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23.5 x 15.88 x 1.91

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Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

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Non-Fiction Computing & I.T.Computer Science Systems Analysis & Design Computer Programming & Software Development Programming & Scripting Languages Engineering & Technology Energy Technology & Engineering Electrical Engineering Mathematics Electronics & Communications Engineering Electronics Engineering

Circuits & Components

Introduction
Related Work
The Static Model
A Well-Formed VHDL Model
The Reduction Algebra
Completeness of the Reduced Form
Interval Temporal Logic
The Dynamic Model
Applications of the Dynamic Model
A Framework for Proving Equivalences Using PVS
Conclusions
Appendices
References
Index
Table of Contents provided by Publisher. All Rights Reserved.

Formal Semantics and Proof Techniques for Optimizing VHDL Models

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Hardcover

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