| Signal Processing | |
| Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing | p. 1 |
| Auditory Signal Processing in Hardware: A Linear Gammatone Filterbank Design for a Model of the Auditory System | p. 11 |
| SONIC - A Plug-In Architecture for Video Processing | p. 21 |
| CAD Tools for DRL | |
| DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems | p. 31 |
| Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework | p. 41 |
| Optimization Studies | |
| Optimal Finite Field Multipliers for FPGAs | p. 51 |
| Memory Access Optimization and RAM Inference for Pipeline Vectorization | p. 61 |
| Analysis and Optimization of 3-D FPGA Design Parameters | p. 71 |
| Physical Design | |
| Tabu Search: Ultra-Fast Placement for FPGAs | p. 81 |
| Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies | p. 91 |
| Hierarchical Interactive Approach to Partition Large Designs into FPGAs | p. 101 |
| Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays | p. 111 |
| Dynamically Reconfigurable Logic | |
| DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems | p. 124 |
| A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic | p. 134 |
| Self Controlling Dynamic Reconfiguration: A Case Study | p. 144 |
| Design Tools | |
| An Internet Based Development Framework for Reconfigurable Computing | p. 155 |
| On Tool Integration in High-Performance FPGA Design Flows | p. 165 |
| Hardware-Software Codesign for Dynamically Reconfigurable Architectures | p. 175 |
| Reconfigurable Computing | |
| Serial Hardware Libraries for Reconfigurable Designs | p. 185 |
| Reconfigurable Computing in Remote and Harsh Environments | p. 195 |
| Communication Synthesis for Reconfigurable Embedded Systems | p. 205 |
| Run-Time Parameterizable Cores | p. 215 |
| Applications | |
| Rendering PostScriptÖ Fonts on FPGAs | p. 223 |
| Implementing PhotoshopÖ Filters in VirtexÖ | p. 233 |
| Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler | p. 243 |
| Quantitative Analysis of Run-Time Reconfigurable Database Search | p. 253 |
| Novel Architectures | |
| An On-Line Arithmetic Based FPGA for Low-Power Custom Computing | p. 264 |
| A New Switch Block for Segmented FPGAs | p. 274 |
| PulseDSP - A Signal Processing Oriented Programmable Architecture | p. 282 |
| Machine Applications | |
| FPGA Viruses | p. 291 |
| Genetic Programming Using Self-Reconfigurable FPGAs | p. 301 |
| Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs | p. 313 |
| Synthia : Synthesis of Interacting Automata Targeting LUT-based FPGAs | p. 323 |
| Short Papers | |
| An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes | p. 333 |
| An FPGA Implementation of Goertzel Algorithm | p. 339 |
| Pipelined Multipliers and FPGA Architectures | p. 347 |
| FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding | p. 353 |
| Reconfigurable Multiplier for Virtex FPGA Family | p. 359 |
| Pipelined Floating Point Arithmetic Optimized for FPGA Architectures | p. 365 |
| SL - A Structural Hardware Design Language | p. 371 |
| High-Level Hierarchical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules | p. 377 |
| Mapping Applications onto Reconfigurable KressArrays | p. 385 |
| Global Routing Models | p. 391 |
| Power Modelling in Field Programmable Gate Arrays (FPGA) | p. 396 |
| NEBULA: A Partially and Dynamically Reconfigurable Architecture | p. 405 |
| High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects | p. 411 |
| AHA-GRAPE: Adaptive Hydrodynamic Architecture - GRAvity PipE | p. 417 |
| DIME - The First Module Standard for FPGA Based High Performance Computing | p. 425 |
| The Proteus Processor - A Conventional CPU with Reconfigurable Functionality | p. 431 |
| Logic Circuit Speeding up through Multiplexing | p. 438 |
| A Wildcarding Mechanism for Acceleration of Partial Configurations | p. 444 |
| Hardware Implementation Techniques for Recursive Calls and Loops | p. 450 |
| A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation | p. 456 |
| An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis | p. 462 |
| Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array's: An Integrated Approach Based on Reconfigurable Virtual Architectures | p. 469 |
| A Concept for an Evaluation Framework for Reconfigurable Systems | p. 475 |
| Debugging Application-Specific Programmable Products | p. 481 |
| IP Validation for FPGAs Using Hardware Object TechnologyÖ | p. 487 |
| A Processor for Artificial Life Simulation | p. 495 |
| A Distributed, Scalable, Multi-Layered Approach to Evolvable System Design Using FPGA's | p. 501 |
| Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching | p. 507 |
| A Reconfigurable Architecture for High Speed Computation by Pipeline Processing | p. 514 |
| Seeking (the right) Problems for the Solutions of Reconfigurable Computing | p. 520 |
| A Runtime Reconfigurable Implementation of the GSAT algorithm | p. 526 |
| Accelerating Boolean Implications with FPGAs | p. 532 |
| Author Index | p. 539 |
| Table of Contents provided by Publisher. All Rights Reserved. |
