| Technology Trends and Adaptive Computing | p. 1 |
| Prototyping Framework for Reconfigurable Processors | p. 6 |
| An Emulator for Exploring RaPiD Configurable Computing Architectures | p. 17 |
| A New Placement Method for Direct Mapping into LUT-Based FPGAs | p. 27 |
| fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits | p. 37 |
| Macrocell Architectures for Product Term Embedded Memory Arrays | p. 48 |
| Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs | p. 59 |
| Memory Synthesis for FPGA-Based Reconfigurable Computers | p. 70 |
| Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic | p. 81 |
| Implementation (Normalised) RLS Lattice on Virtex | p. 91 |
| Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing | p. 101 |
| Static Profile-Driven Compilation for FPGAs | p. 112 |
| Synthesizing RTL Hardware from Java Byte Codes | p. 123 |
| PuMA++: From Behavioral Specification to Multi-FPGA-Prototype | p. 133 |
| Secure Configuration of Field Programmable Gate Arrays | p. 142 |
| Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm | p. 152 |
| JBits Implementations of the Advanced Encryption Standard (Rijndael) | p. 162 |
| Task-Parallel Programming of Reconfigurable Systems | p. 172 |
| Chip-Based Reconfigurable Task Management | p. 182 |
| Configuration Caching and Swapping | p. 192 |
| Multiple Stereo Matching Using an Extended Architecture | p. 203 |
| Implementation of a NURBS to Bezier Conversor with Constant Latency | p. 213 |
| Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems | p. 223 |
| Processing Models for the Next Generation Network | p. 232 |
| Tightly Integrated Placement and Routing for FPGAs | p. 233 |
| Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays | p. 243 |
| Reconfigurable Router Modules Using Network Protocol Wrappers | p. 254 |
| Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware | p. 264 |
| The MOLEN [rho][mu]-Coded Processor | p. 275 |
| Run-Time Optimized Reconfiguration Using Instruction Forecasting | p. 286 |
| CRISP: A Template for Reconfigurable Instruction Set Processors | p. 296 |
| Evaluation of an FPGA Implementation of the Discrete Element Method | p. 306 |
| Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers | p. 315 |
| A Reconfigurable Embedded Input Device for Kinetically Challenged Persons | p. 326 |
| Bubble Partitioning for LUT-Based Sequential Circuits | p. 336 |
| Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits | p. 346 |
| Placing, Routing, and Editing Virtual FPGAs | p. 357 |
| Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver | p. 367 |
| A Music Synthesizer for FPGA | p. 377 |
| Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders | p. 388 |
| Loop Tiling for Reconfigurable Accelerators | p. 398 |
| The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems | p. 409 |
| A n-Bit Reconfigurable Scalar Quantiser | p. 420 |
| Real Time Morphological Image Contrast Enhancement in Virtex FPGA | p. 430 |
| Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing | p. 441 |
| Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware | p. 451 |
| The Evolution of Programmable Logic: Past, Present, and Future Predictions | p. 461 |
| Dynamically Reconfigurable Cores | p. 462 |
| Reconfigurable Breakpoints for Co-debug | p. 473 |
| Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification | p. 483 |
| FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits | p. 493 |
| A Generic Library for Adaptive Computing Environments | p. 503 |
| Generative Development System for FPGA Processors with Active Components | p. 513 |
| Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines | p. 523 |
| System Level Tools for DSP in FPGAs | p. 534 |
| Parameterized Function Evaluation for FPGAs | p. 544 |
| Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures | p. 555 |
| A Digit-Serial Structure for Reconfigurable Multipliers | p. 565 |
| FPGA Resource Reduction Through Truncated Multiplication | p. 574 |
| Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures | p. 584 |
| An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars | p. 590 |
| Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach | p. 595 |
| An Approach to Real-Time Visualization of PIV Method with FPGA | p. 601 |
| FPGA-Based Discrete Wavelet Transforms System | p. 607 |
| X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor | p. 613 |
| Arithmetic Operation Oriented Reconfigurable Chip: RHW | p. 618 |
| Initial Analysis of the Proteus Architecture | p. 623 |
| Building Asynchronous Circuits with JBits | p. 628 |
| Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux | p. 633 |
| A Reconfigurable Approach to Packet Filtering | p. 638 |
| FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding | p. 643 |
| A Data Re-use Based Compiler Optimization for FPGAs | p. 648 |
| Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware | p. 653 |
| A System on Chip for Power Line Communications According to European Home Systems Specifications | p. 658 |
| Author Index | p. 663 |
| Table of Contents provided by Blackwell. All Rights Reserved. |