| Acknowledgments | p. xix |
| Running Start | p. 1 |
| About This Book | p. 2 |
| Some Words to Know | p. 3 |
| What's a Chip? | p. 3 |
| What's Silicon? | p. 3 |
| What's a Semiconductor? | p. 4 |
| What's a Transistor? | p. 4 |
| What's an IC? | p. 5 |
| What's a Component? | p. 5 |
| What's a Circuit? | p. 6 |
| Semiconductor Family Tree | p. 7 |
| Semiconductor Family Tree | p. 8 |
| From Little Acorns to Great Oak Trees | p. 9 |
| Integrated Circuits versus Discrete Components | p. 11 |
| Digital versus Analog Components | p. 12 |
| Simple Analog Components | p. 13 |
| Resistors | p. 14 |
| Capacitors | p. 15 |
| Inductors | p. 16 |
| Transistors | p. 17 |
| Diodes | p. 19 |
| LEDs | p. 19 |
| Laser Diodes | p. 21 |
| Optical Sensors | p. 22 |
| Advanced Analog Components | p. 22 |
| CCD Image Sensors | p. 22 |
| Other Sensors | p. 23 |
| A/D and D/A Converters | p. 23 |
| MEMS | p. 24 |
| Medium-Scale Digital Chips | p. 25 |
| Logic Gates | p. 25 |
| Highly Integrated Digital Chips | p. 27 |
| Memory Chips | p. 27 |
| Communications Chips | p. 28 |
| Graphics Chips | p. 28 |
| Peripherals | p. 29 |
| Custom Chips: ASICs and ASSPs | p. 30 |
| Programmable Logic Chips | p. 31 |
| Microprocessors | p. 32 |
| How Chips Are Designed | p. 35 |
| Old-Style Design Process | p. 36 |
| New-Style Design Process | p. 37 |
| EDA Design Tools | p. 37 |
| Schematic Capture | p. 38 |
| Hardware Synthesis | p. 39 |
| Hardware-Description Languages | p. 41 |
| The HDL Leaders: VHDL and Verilog | p. 42 |
| Alternate HDLs | p. 44 |
| Producing a Netlist | p. 45 |
| Floor Planning | p. 45 |
| Place and Route | p. 46 |
| Verifying the Design Works | p. 48 |
| C Modeling | p. 49 |
| Hardware Simulation | p. 50 |
| Hardware Emulation Boxes | p. 50 |
| Using Outside IP | p. 51 |
| Hard and Soft IP Cores | p. 52 |
| Physical Libraries | p. 54 |
| Getting to Tape Out and Film | p. 54 |
| Current Problems and Future Trends | p. 55 |
| How Chips Are Made | p. 59 |
| Clean Rooms and Fabs | p. 60 |
| Developing Technology: Chips and Photography | p. 62 |
| Silicon Ingots to Start | p. 62 |
| Polishing the Wafer Smooth | p. 64 |
| Building the Layer Cake | p. 64 |
| Laser Surgery: Etching Away the Transistors | p. 65 |
| Step and Repeat | p. 67 |
| Etching Bath | p. 69 |
| Ready for the Metal Round | p. 70 |
| Testing Phase I | p. 71 |
| Bringing out the Diamonds | p. 72 |
| Sorting the Fast From the Merely Good | p. 72 |
| Wrap It Up | p. 73 |
| How Many Nanometers in a Micron? | p. 74 |
| Let's Get Small | p. 76 |
| Business and Markets | p. 79 |
| Worldwide Production of Semiconductors | p. 80 |
| Sales by Revenue | p. 82 |
| Sales by Unit | p. 83 |
| Average Selling Prices | p. 84 |
| Average Microprocessor Prices | p. 86 |
| Geographic Breakdown of Production | p. 87 |
| Worldwide Consumption of Semiconductors | p. 89 |
| Computers and PCs | p. 90 |
| Communications and Networking | p. 91 |
| Consumer Electronics | p. 92 |
| Industrial Electronics | p. 93 |
| Automotive Electronics | p. 94 |
| Military Electronics | p. 95 |
| The Business of Making Semiconductors | p. 96 |
| Semiconductor Food Chain | p. 96 |
| Independent Device Manufacturer | p. 96 |
| Fabless Chip Company | p. 97 |
| Pure-Play Foundries | p. 98 |
| Materials In, Distributors Out | p. 98 |
| Facilities and Equipment | p. 99 |
| Manufacturing Equipment | p. 101 |
| Fab Utilization | p. 102 |
| Silicon Cost Model | p. 104 |
| Wafer Cost | p. 105 |
| Gross Die per Wafer | p. 108 |
| Defects and Yield | p. 109 |
| Packaging and Testing | p. 111 |
| Economics of Updating Fabs | p. 111 |
| Economics of Larger Wafers | p. 113 |
| Economic Summary | p. 114 |
| Essential Guide to Microprocessors | p. 119 |
| Overview of Microprocessors | p. 120 |
| Microprocessors Everywhere | p. 121 |
| What Are Embedded Processors? | p. 122 |
| Microprocessor History and Evolution | p. 123 |
| What's a Processor Architecture? | p. 126 |
| RISC and CISC Architecture | p. 126 |
| DSP Architecture | p. 127 |
| Superscalar Architecture | p. 128 |
| VLIW Architecture | p. 128 |
| Microprocessor Anatomy and Gazetteer | p. 129 |
| Decoder | p. 129 |
| Execution Unit | p. 129 |
| Floating-Point Unit | p. 131 |
| Registers | p. 131 |
| Cache | p. 132 |
| Bus | p. 133 |
| Pipeline | p. 134 |
| What Do 4-Bit, 8-Bit, 16-Bit, and 32-Bit Mean? | p. 134 |
| Performance, Benchmarks, and Gigahertz | p. 137 |
| Misleading MIPS | p. 138 |
| The Mythical MIPS-per-MHz Ratio | p. 139 |
| Power Consumption and MIPS/Watt | p. 140 |
| What Is Software? | p. 141 |
| Choosing Microprocessors | p. 143 |
| Software Compatibility | p. 143 |
| Microprocessor Future Trends | p. 144 |
| Essential Guide to Memory | p. 147 |
| Overview of Memory Chips | p. 148 |
| About Memory Chips | p. 148 |
| Types of Memory | p. 150 |
| Nonvolatile ROM | p. 151 |
| Masked ROM | p. 151 |
| Programmable ROM | p. 151 |
| Erasable Programmable ROM | p. 152 |
| Electrically Erasable Programmable ROM | p. 153 |
| Flash ROM | p. 153 |
| Volatile RAM | p. 154 |
| SRAM | p. 155 |
| DRAM | p. 155 |
| Memory Interfaces | p. 156 |
| Future Memories | p. 157 |
| Essential Guide to Custom and Configurable Chips | p. 159 |
| Overview of Custom Chips | p. 160 |
| About Custom Chips | p. 160 |
| Field-Programmable Chips | p. 160 |
| Custom ASIC Chips | p. 163 |
| To ASIC or Not To ASIC | p. 163 |
| Designing an ASIC | p. 164 |
| Full-Custom Designs | p. 165 |
| Standard Cell Designs | p. 165 |
| Gate Array Designs | p. 166 |
| Building an ASIC | p. 166 |
| Dynamically Reconfigurable Chips | p. 167 |
| About Dynamically Reconfigurable Logic | p. 168 |
| Intellectual Property Licensing | p. 169 |
| IP Licensing Business | p. 170 |
| IP Revenue Streams | p. 171 |
| IP Summary | p. 172 |
| Future Outlook for Custom Chips | p. 173 |
| Theory | p. 177 |
| Digital and Binary Concepts | p. 178 |
| Gates and Logic Functions | p. 180 |
| Logic, Binary, and Digital Concepts | p. 181 |
| NOT Gate | p. 182 |
| AND Gate | p. 182 |
| OR Gate | p. 184 |
| Exclusive-OR | p. 186 |
| Inverted Gates | p. 186 |
| How Transistors Work | p. 188 |
| About Electrons and Electronics | p. 190 |
| Standards Bodies and Reference | p. 193 |
| Standards Bodies and Organizations | p. 194 |
| Semiconductor Industry of America (SIA) | p. 194 |
| World Semiconductor Trade Statistics (WSTS) | p. 194 |
| Sematech | p. 194 |
| Semiconductor Equipment and Materials International (SEMI) | p. 195 |
| Joint Electron Device Engineering Council (JEDEC) | p. 195 |
| Electronic Industries Alliance (EIA) | p. 195 |
| Electronic Design Automation Consortium (EDAC) | p. 195 |
| Institute of Electrical and Electronics Engineers (IEEE) | p. 196 |
| Institution of Electrical Engineers (IEE) | p. 196 |
| International Engineering Consortium (IEC) | p. 196 |
| International Symposium on Quality Electronic Design (ISQED) | p. 196 |
| Accellera | p. 197 |
| Open SystemC Initiative (OSCI) | p. 197 |
| Conferences and Trade Shows | p. 197 |
| Asilomar Conference on Signals, Systems, and Computers ("Asilomar") | p. 197 |
| Embedded Systems Conference (ESC) | p. 197 |
| Microprocessor Forum | p. 198 |
| Embedded Processor Forum | p. 198 |
| Network Processor Conference | p. 198 |
| Hot Chips | p. 198 |
| International Solid State Circuits Conference (ISSCC) | p. 199 |
| International Electron Devices Meeting (IEDM) | p. 199 |
| Other Resources | p. 199 |
| The Tech Museum of Innovation ("The Tech") | p. 199 |
| Computer History Museum | p. 200 |
| Sematech Online Dictionary | p. 200 |
| Electronic Design & Technology News Online Encyclopedia | p. 200 |
| Microprocessor Report | p. 200 |
| Dynamic Silicon | p. 200 |
| Electronic Engineering Times | p. 200 |
| Glossary | p. 201 |
| Index | p. 211 |
| Table of Contents provided by Syndetics. All Rights Reserved. |