Error Correction Codes for Non-Volatile Memories

Preface. Acknowledgements. 1. Basic coding theory. 1.1 Introduction. 1.2 Error detection and correction codes. 1.3 Probability of errors in a transmission channel. 1.4 ECC effect on error probability. 1.5 Basic definitions. Bibliography. 2 Error Correction Codes. 2.1 Hamming codes. 2.2 Reed-Muller codes. 2.3 Cyclic codes. Bibliography. 3 NOR Flash memories. 3.1 Introduction. 3.2 Read. 3.3 Program. 3.4 Erase. Bibliography. 4 NAND Flash memories. 4.1 Introduction. 4.2 Read. 4.3 Program. 4.4 Erase. Bibliography. 5 Reliability of Floating Gate Memories; A.Chimenton, M.Atti, P.Olivo. 5.1 Introduction. 5.2 Reliability issues in floating gate memories. 5.3 Conclusions. Bibliography. 6 Hardware implementation of Galois field operators. 6.1 Gray map. 6.2 Adders. 6.3 Constant multipliers. 6.4 Full multipliers. 6.5 Divider. 6.6 Linear Shift Register. Bibliography. 7 Hamming code for Flash memories. 7.1 Introduction. 7.2 NOR Single Bit. 7.3 NOR Flash multilevel memory. 7.4 Algorithmic Hamming code for big size blocks. Bibliography. 8 Cyclic codes for non volatile storage. 8.1 General structure. 8.2 Encoding. 8.3 Syndromes calculation. 8.4 Finding error locator polynomial. 8.5 Searching polynomial roots. 8.6 Computing error magnitude. 8.7 Decoding failures. 8.8 BCH vs Reed-Solomon. Bibliography. 9 BCH hardware implementation in NAND Flash memories. 9.1 Introduction. 9.2 Scaling of a ECC for MLC memories. 9.3 The system. 9.4 Parity computation. 9.5 Syndrome computation. 9.6 Berlekamp machine. 9.7 The Chien Machine. 9.8 Double Chien machine. 9.9 BCH embedded into the NAND memory. Bibliography. 10 Erasure technique. 10.1 Error disclosing capability for binary BCH codes. 10.2 Erasure concept in memories. 10.3 Binary erasure decoding. 10.4 Erasure and majority decoding. 10.5 Erasure decoding performances. Bibliography. Appendix A: Hamming code. A.1 Routine to find a parity matrix for a single bit or a single cell correction. A.2 Routine to find a parity matrix for a two errors correction code. A.3 Routine to find a parity matrix to correct 2 erroneous cells. Appendix B: BCH code. B.1 Routine to generate the BCH code parameters. B.2 Routine to encode a message. B.3 Routine to calculate the syndromes of a read message. B.4 Routine to calculate the evaluation matrices. B.5 Routines to compute operations in a Galois field. B.6 Routine to calculate the lambda coefficients. B.7 Routine to execute Chien algorithm. B.8 Routine to find the matrix to execute the multiplication by alpha. Appendix C: the Galois field GF(24). Appendix D: the parallel BCH code. D.1 Routine to get the matrix for the encoding. D.2 Routine to get matrices for the syndromes. D.3 Routine to get the matrix for the multiplier. D.4 Routine to calculate the coefficients of the error locator polynomial. D.5 Routine to get matrices for the Chien machine. D.6 Global matrix optimization for the Chien machine. D.7 BCH flow overview. Appendix E: erasure decoding technique. E.1 Subroutines. E.2 Erasure decoding routine. Index.