| Preface | p. xi |
| Conference Committee | p. xv |
| Validation and Verification | |
| Requirements and Concepts for Transaction Level Assertion Refinement | p. 1 |
| Using a Runtime Measurement Device with Measurement-Based WCET Analysis | p. 15 |
| Implementing Real-Time Algorithms by using the AAA Prototyping Methodology | p. 27 |
| Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities | p. 37 |
| Approach for a Formal Verification of a Bit-serial Pipelined Architecture | p. 47 |
| Automotive Applications | |
| Automotive System Optimization using Sensitivity Analysis | p. 57 |
| Towards a Dynamically Reconfigurable Automotive Control System Architecture | p. 71 |
| An OSEK/VDX-based Multi-JVM for Automotive Appliances | p. 85 |
| Towards Dynamic Load Balancing for Distributed Embedded Automotive Systems | p. 97 |
| Hardware Synthesis | |
| Automatic Data Path Generation from C code for Custom Processors | p. 107 |
| Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures | p. 121 |
| An Interactive Design Environment for C-based High-Level Synthesis | p. 135 |
| Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning | p. 145 |
| Embedded Vertex Shader in FPGA | p. 155 |
| Specification and Partitioning | |
| A Hybrid Approach for System-Level Design Evaluation | p. 165 |
| Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs | p. 179 |
| An Interactive Model Re-Coder for Efficient SoC Specification | p. 193 |
| Constrained and Unconstrained Hardware-Software Partitioning using Particle Swarm Optimization Technique | p. 207 |
| Design Methodologies | |
| Using Aspect-Oriented Concepts in the Requirements Analysis of Distributed Real-Time Embedded Systems | p. 221 |
| Smart Speed TechnologyÖ | p. 231 |
| Embedded Software | |
| Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services | p. 241 |
| Reducing the Code Size of Retimed Software Loops under Timing and Resource Constraints | p. 255 |
| Identification and Removal of Program Slice Criteria for Code Size Reduction in Embedded Systems | p. 269 |
| Configurable Hybridkernel for Embedded Real-Time Systems | p. 279 |
| Embedded Software Development in a System-Level Design Flow | p. 289 |
| Network on Chip | |
| Data Reuse Driven Memory and Network-On-Chip Co-Synthesis | p. 299 |
| Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions | p. 313 |
| Hardware Implementation of the Time-Triggered Ethernet Controller | p. 325 |
| Error Containment in the Time-Triggered System-On-a-Chip Architecture | p. 339 |
| Medical Applications | |
| Generic Architecture Designed for Biomedical Embedded Systems | p. 353 |
| A Small High Performance Microprocessor Core Sirius for Embedded Low Power Designs, Demonstrated in a Medical Mass Application of an Electronic Pill (EPill“) | p. 363 |
| Distributed and Network Systems | |
| Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes | p. 373 |
| Dynamic Software Update of Resource-Constrained Distributed Embedded Systems | p. 387 |
| Configurable Medium Access Control for Wireless Sensor Networks | p. 401 |
| Integrating Wireless Sensor Networks and the Grid through POP-C++ | p. 411 |
| Panel | |
| Modeling of Software-Hardware Complexes | p. 421 |
| Modeling of Software-Hardware Complexes | p. 423 |
| Enhancing a Real-Time Distributed Computing Component Model through Cross-Fertilization | p. 427 |
| Modeling of Software-Hardware Complexes | p. 431 |
| Software-Hardware Complexes: Towards Flexible Borders | p. 433 |
| Tutorials | |
| Embedded SW Design Space Exploration and Automation using UML-Based Tools | p. 437 |
| Medical Embedded Systems | p. 441 |
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