Embedded Computer Systems: Architectures, Modeling, and Simulation

5th International Workshop, Samos 2005, Samos, Greece, July 18-20, Proceedings

By: Timo D. HÃ¤mÃ¤lÃ¤inen (Editor), Andy D. Pimentel (Editor), Jarmo Takala (Editor)

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Paperback | 4 July 2005

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The SAMOS workshop is an international gathering of highly quali?ed researchers from academia and industry, sharing in a 3-day lively discussion on the quiet and - spiring northern mountainside of the Mediterranean island of Samos. As a tradition, the workshop features workshop presentations in the morning, while after lunch all kinds of informal discussions and nut-cracking gatherings take place. The workshop is unique in the sense that not only solved research problems are presented and discussed but also (partly) unsolved problems and in-depth topical reviews can be unleashed in the sci- ti?c arena. Consequently, the workshop provides the participants with an environment where collaboration rather than competition is fostered. The earlier workshops, SAMOS I-IV (2001-2004), were composed only of invited presentations. Due to increasing expressions of interest in the workshop, the Program Committee of SAMOS V decided to open the workshop for all submissions. As a result the SAMOS workshop gained an immediate popularity; a total of 114 submitted papers were received for evaluation. The papers came from 24 countries and regions: Austria (1), Belgium (2), Brazil (5), Canada (4), China (12), Cyprus (2), Czech Republic (1), Finland (15), France (6), Germany (8), Greece (5), Hong Kong (2), India (2), Iran (1), Korea (24), The Netherlands (7), Pakistan (1), Poland (2), Spain (2), Sweden (2), T- wan (1), Turkey (2), UK (2), and USA (5). We are grateful to all of the authors who submitted papers to the workshop.

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Platform thinking in embedded systems	p. 1
Interprocedural optimization for dynamic hardware configurations	p. 2
Reconfigurable embedded systems : an application-oriented perspective on architectures and design techniques	p. 12
Reconfigurable multiple operation array	p. 22
RAPANUI : rapid prototyping for media processor architecture exploration	p. 32
Data-driven regular reconfigurable arrays : design space exploration and mapping	p. 41
Automatic FIR filter generation for FPGAs	p. 51
Two-dimensional fast cosine transform for vector-STA architectures	p. 62
Configurable computing for high-security/high-performance ambient systems	p. 72
FPL-3E : towards language support for reconfigurable packet processing	p. 82
Flux caches : what are they and are they useful?	p. 93
First-level instruction cache design for reducing dynamic energy consumption	p. 103
A novel JAVA processor for embedded devices	p. 112
Formal specification of a protocol processor	p. 122
Tuning a protocol processor architecture towards DSP operations	p. 132
Observations on power-efficiency trends in mobile communication devices	p. 142
CORDIC-augmented sandbridge processor for channel equalization	p. 152
Power-aware branch logic : a hardware based technique for filtering access to branch logic	p. 162
Exploiting intra-function correlation with the global history stack	p. 172
Power efficient instruction caches for embedded systems	p. 182
Micro-architecture performance estimation by formula	p. 192
Offline phase analysis and optimization for multi-configuration processors	p. 202
Hardware cost estimation for application-specific processor design	p. 212
Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures	p. 222
Generating stream based code from plain C	p. 232
Fast real-time job selection with resource constraints under earliest deadline first	p. 242
A programming model for an embedded media processing architecture	p. 251
Automatic ADL-based assembler generation for ASIP programming support	p. 262
Sandbridge software tools	p. 269
A hardware accelerator for controlling access to multiple-unit resources in safety/time-critical systems	p. 279
Pattern matching acceleration for network intrusion detection systems	p. 289
Real-time stereo vision on a reconfigurable system	p. 299
Application of very fast simulated reannealing (VFSR) to low power design	p. 308
Compressed swapping for NAND flash memory based embedded systems	p. 314
A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms	p. 324
A scalable embedded JPEG2000 architecture	p. 334
A routing paradigm with novel resources estimation and routability models for X-architecture based physical design	p. 344
Benchmarking mesh and hierarchical bus networks in system-on-chip context	p. 354
DDM-CMP : data-driven multithreading on a chip multiprocessor	p. 364
Modeling NoC architectures by means of deterministic and stochastic petri nets	p. 374
High abstraction level design and implementation framework for wireless sensor networks	p. 384
The ODYSSEY tool-set for system-level synthesis of object-oriented models	p. 394
Design and implementation of a WLAN terminal using UML 2.0 based design flow	p. 404
Rapid implementation and optimisation of DSP systems on SoPC heterogeneous platforms	p. 414
DVB-DSNG modem high level synthesis in an optimized latency insensitive system context	p. 424
SystemQ : a queuing-based approach to architecture performance evaluation with SystemC	p. 434
Moving up to the modeling level for the transformation of data structures in embedded multimedia applications	p. 445
A case for visualization-integrated system-level design space exploration	p. 455
Mixed virtual/real prototypes for incremental system design - a proof of concept	p. 465
Table of Contents provided by Blackwell. All Rights Reserved.

Embedded Computer Systems: Architectures, Modeling, and Simulation

5th International Workshop, Samos 2005, Samos, Greece, July 18-20, Proceedings

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