| Dedication | p. v |
| List of Figures | p. xiii |
| Foreword | p. xvii |
| Preface | p. xix |
| Acknowledgments | p. xxiii |
| Starting the Verification Journey | |
| An Introduction to IC Verification | p. 3 |
| Importance of Verification | p. 3 |
| Overview of a Typical ASIC Design Process | p. 6 |
| Factors in Successful Verification | p. 11 |
| References | p. 12 |
| Approaches to Verification | p. 13 |
| What is Functional Verification all About? | p. 14 |
| Stimulating the design - A choice of approaches | p. 16 |
| Black Box Approach | p. 16 |
| White Box Approach | p. 18 |
| Gray Box Approach | p. 18 |
| Verification Approaches Based on Integration | p. 19 |
| Block Level Verification | p. 20 |
| Sub System Verification | p. 23 |
| Full Chip Verification | p. 25 |
| System Level Verification | p. 26 |
| Instruction Driven Verification | p. 26 |
| Random Testing | p. 29 |
| Coverage Driven Verification | p. 30 |
| Transaction Based Verification | p. 33 |
| Golden Model Approach | p. 37 |
| Advantages of a Golden Model | p. 37 |
| Disadvantages of using a Golden Model | p. 38 |
| Pre-Post Processing Approach | p. 39 |
| Assertion Based Verification | p. 42 |
| Assertions - Who writes them and when? | p. 44 |
| Types of Assertions | p. 45 |
| Advantages of an Assertion Based Methodology | p. 45 |
| Challenges with an Assertion Based Methodology | p. 48 |
| Formal Verification | p. 49 |
| Model Checking | p. 51 |
| A Comparison of Simulation and Formal approaches | p. 52 |
| Emulation and Acceleration | p. 54 |
| References | p. 57 |
| Various Workflows Practiced in Verification | p. 59 |
| An Overview of the Entire Verification Process | p. 59 |
| The Planning Process | p. 62 |
| Some Other Aspects of Verification Planning | p. 63 |
| Verification Resource Planning | p. 64 |
| The Regression Process | p. 65 |
| Block Regressions | p. 67 |
| Chip Level Regressions | p. 68 |
| Coverage in Regressions | p. 68 |
| Maturing of the Design | p. 69 |
| The Periodic Review Process | p. 70 |
| Regression Result Reviews | p. 71 |
| The Verification Signoff Process | p. 72 |
| Ingredients of Successful Verification | |
| People make all the Difference | p. 77 |
| Team Dynamics and Team Habits for Success | p. 78 |
| Begin With the Big Picture in Mind | p. 78 |
| Do it Right the First Time | p. 80 |
| Be Object Oriented in your Approach | p. 82 |
| Reduce, Reuse and Recycle | p. 82 |
| Innovate | p. 83 |
| Communicate | p. 84 |
| The Six Qualities of Successful Verification Engineers | p. 86 |
| The Ability to see the Full Picture | p. 87 |
| Assumes Nothing | p. 88 |
| Consistent | p. 88 |
| Organized | p. 89 |
| Multi-skilled | p. 89 |
| Empower Others | p. 90 |
| References | p. 91 |
| Case Studies from the Real World | p. 93 |
| Block and System Level Tests use Unrelated Environments | p. 94 |
| Not Implementing Monitors and Assertions Early on | p. 94 |
| Review Processes Not Done Timely | p. 95 |
| Pure Random Testing Without Directed Tests | p. 96 |
| Not Running a Smoke Test Before a Regression | p. 97 |
| Lint Policies | p. 98 |
| Effective Use of a Source Control Strategy | p. 98 |
| Tracking Results That Matter | p. 101 |
| Why Do We Ever Need any Verification Metrics? | p. 101 |
| Metrics in a Regression | p. 102 |
| Commonly used Metrics | p. 105 |
| Functional Coverage Metrics | p. 109 |
| Structural Coverage Metrics | p. 110 |
| Some Caveats on Structural Coverage | p. 111 |
| Assertion Verification Metrics | p. 111 |
| References | p. 113 |
| Reducing work in Verification | |
| Reducing Work in Verification | p. 117 |
| Considerations in a Verification Environment | p. 118 |
| Tri-State Buses and Dealing with Them | p. 119 |
| Dealing with Internal Signals | p. 120 |
| Environmental Considerations | p. 122 |
| Dealing with Register Programming | p. 128 |
| A Hybrid Approach to Register Programming | p. 131 |
| Dealing with Clocks | p. 136 |
| Driving the Design | p. 137 |
| Debugging the Design | p. 138 |
| Making Note of Errors | p. 141 |
| Debug Levels | p. 141 |
| Code Profiling to Keep the Inefficiency Out | p. 143 |
| Regression Management | p. 145 |
| Identify Failures Before You Run Again | p. 149 |
| Don't Postpone Features to be Tested | p. 149 |
| Compile your Code | p. 149 |
| QC Processes to run a Clean Run | p. 150 |
| Using a Data Profile to Speed up Simulations | p. 150 |
| Getting the Machine to Document for You | p. 154 |
| Keeping an Eye on the Design - Monitors | p. 158 |
| Checkers in an Environment | p. 160 |
| Linting Code | p. 162 |
| The RTL Acceptance Criterion | p. 163 |
| References | p. 164 |
| Ten Steps to Success | |
| Ten Steps to Success | p. 167 |
| A Specification Review | p. 173 |
| The Identification of Test Objects | p. 176 |
| Review of the Test Object List | p. 180 |
| Tagging the List of Test Objects | p. 182 |
| Using Tags to Simplify the Regression Process | p. 183 |
| Test Case Identification | p. 185 |
| Structure of a Test Case | p. 185 |
| Test Case Classifications | p. 188 |
| Directed Tests | p. 188 |
| Sweep Test Cases | p. 190 |
| Negative Testing | p. 192 |
| Random Test Cases | p. 193 |
| The Creation of a Possible List of Test Cases | p. 194 |
| Partitioning of Tests between Block and Top Level | p. 197 |
| The Definition of a Correctness Strategy | p. 200 |
| Data Checkers | p. 200 |
| Protocol Checkers | p. 201 |
| Interface Checkers | p. 201 |
| Cycle Accurate Checkers | p. 203 |
| Using Monitors | p. 203 |
| Using Assertions and Formal Verification in the Methodology | p. 203 |
| The test strategy | p. 206 |
| Hierarchical Strategy | p. 208 |
| Reuse Strategy | p. 210 |
| Stimulus Strategy | p. 210 |
| Test Case Strategy | p. 211 |
| Identifying Test cases for Maximum Yield & Coverage | p. 211 |
| Testing the design | p. 215 |
| Component identification | p. 215 |
| Getting the Job Done. Execution of the test plan | p. 221 |
| Getting a Helping Hand from External Resources | p. 222 |
| The Case for GATE Simulations | p. 223 |
| Figuring out where you Are in the Process | p. 226 |
| Performing Hole Analysis of What got Left Out in the Test Plan | p. 231 |
| The (bi)Weekly Review Processes | p. 232 |
| The monthly Review Processes | p. 237 |
| Correlations on completion to sign-off | p. 238 |
| References and Additional reading | p. 242 |
| Glossary | p. 243 |
| Appendices | p. 244 |
| Using PERL to connect to Microsoft Excel and Access | p. 245 |
| Using PERL to convert between UNIX text files and Microsoft Word | p. 249 |
| About the Author | p. 253 |
| Index | p. 255 |
| Table of Contents provided by Ingram. All Rights Reserved. |