Dynamically Reconfigurable Systems

Part I Architectures. 1 Development and synthesis of adaptive multi-grained reconfigurable hardware architecture for dynamic function patterns; A.Thomas, J.Becker. 1.1 Introduction. 1.2 HoneyComb architecture. 1.3 Tool Support. 1.4 Future Work. 1.5 Conclusion. References. 2 Reconfigurable components for application-specific processor architectures; T.G. Noll, T.von Sydow, B.Neumann, J.Schleifer, T.Coenen, G.Kappen. 2.1 Introduction. 2.2 Parameterized eFPGA Target Architecture. 2.3 Physical Implementation of Application Class Specific eFPGAs. 2.4 Mapping and Configuration. 2.5 Examples of (Stand Alone) eFPGAs as SoC Building Blocks. 2.6 Examples of eFPGAs as Coprocessors to Standard RISC Processor Kernels. 2.7 Conclusion. References. 3 Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform; J.Angermeier, C.Bobda, M.Majer, J.Teich. 3.1 Introduction. 3.2 Drawbacks of existing dynamically reconfigurable systems. 3.3 The Erlangen Slot Machine. 3.4 Inter-module Communications. 3.5 Reconfiguration Manager. 3.6 Case Study: Video and audio streaming. 3.7 Usage of the ESM in different fields. 3.8 Conclusions. References. Part II Design Methods and Tools -- Modeling, Evaluation and Compilation 4 Models and Algorithms for Hyperreconfigurable Hardware; S.Lange, M.Middendorf. 4.1 Introduction. 4.2 Hyperreconfigurable Machines. 4.3 Example Architectures and Test Cases. 4.4 The Partition into Hypercontexts Problem. 4.5 Diverse Granularity in Multi-level Reconfigurable Systems. 4.6 Partial Reconfiguration and Hyperreconfiguration. 4.7 Conclusions. References. 5 Evaluation and Design Methods for Processor-Like Reconfigurable Architectures; S.Eisenhardt, T.Schweizer, J.Oliveira Filho, T.Kuhn, W.Rosenstiel. 5.1 Introduction. 5.2 Benefits and Costs of Processor-Like Reconfiguration. 5.3 Specialization / Instruction Set Extension. 5.4 Optimizing Power. 5.5 Optimizing External Reconfiguration . 5.6 Conclusion. References. 6 Adaptive Computing Systems and their Design Tools; A.Koch. 6.1 Introduction. 6.2 Execution Model. 6.3 ACS Architecture. 6.4 Hardware/Software Co-Compilation Flow. 6.5 Infrastructure. 6.6 Lessons Learned. 6.7 Future Work. 6.8 Conclusions. References. 7 POLYDYN-- Object-oriented modelling and synthesis targeting dynamically reconfigurable FPGAs; A.Schallenberg, W.Nebel, A.Herrholz, P.A. Hartmann, K.Gruttner, F.Oppenheimer. 7.1 Introduction. 7.2 Related work. 7.3 Methodology. 7.4 Derived interface classes. 7.5 Modelling example: Car audio system. 7.6 Synthesising OSSS+R. 7.7 Evaluation. 7.8 Conclusion and Future Work. References. Part III Design Methods and Tools -- Optimization and Runtime Systems 8 Design Methods and Tools for Improved Partial Dynamic Reconfiguration; M.Rullmann, R.Merker. 8.1 Introduction. 8.2 Motivation. 8.3 Reconfigurable Module Architecture and Partitioning. 8.4 Reconfiguration State Graph. 8.5 Module Mapping and Virtual Architecture. 8.6 High-Level Synthesis of Reconfigurable Modules. 8.7 Experiments. 8.8 System Design for Efficient Partial Dynamic Reconfiguration. References. 9 Dynamic Partial Reconfiguration by Means of Algorithmic Skeletons -- A Case Study --; N.Montealegre, F.J. Rammig. 9.1 Introduction. 9.2 Overview of the overall system. 9.3 Library of Algorithmic Skeletons. 9.4 Application Scenario: Channel Vocoder Analyzer. 9.5 Conclusion. References. 10 ReCoNodes -- Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices; A.Ahmadinia, J.Angermeier, S.P. Fekete, T.Kamphans, D.Koch, M.Majer, N.Schweer, J.Teich, C.Tessars, J.C. van der Veen. 10.1 Introduction. 10.2 Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. 10.3 Minimizing Communication Cost for Reconfigurable Slot Modules. 10.4 No-Break Dynamic Defragmentation of Reconfigurable Devices. 10.5 Scheduling Dynamic Resource Requests. References. 11 ReCoNets -- Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections; C.Haubelt, D.Koch, F.Reimann, T.Steichert, J.Teich. 11.1 Introduction. 11.2 System Model. 11.3 A Distributed Operating System Architecture for Networked Embedded Systems. 11.4 Design and Synthesis of ReCoNets. 11.5 Demonstrator . References. 12 Adaptive runtime system with intelligent allocation of dynamically reconfigurable function model and optimized interface topologies; L.Braun, T.Schwalb, P.Graf, M.Hubner, M.Ullmann, K.D.Muller-Glaser, J.Becker. 12.1 Introduction. 12.2 Partial and dynamic Reconfigration. 12.3 Network on Chip. 12.4 On demand system adaption. 12.5 System modelling. 12.6 Tool chain. 12.7 Model debugging. 12.8 Test. 12.9 Conclusions. References. 13 ReconOS: An Operating System for Dynamically Reconfigurable Hardware; E.Lubbers, M.Platzner. 13.1 Introduction . 13.2 Related Work. 13.3 Programming Model. 13.4 Run-Time System. 13.5 Implementation. 13.6 Experimental measurements. 13.7 Conclusion and Outlook. Part IV Applications 14 FlexiChaP: A Dynamically Reconfigurable ASIP for Channel Decoding for Future Mobile Systems; M.Alles, T.Vogt, C.Brehm, N.Wehn. 14.1 Introduction. 14.2 Channel Codes. 14.3 Decoder Requirements. 14.4 ASIP Design Methodologies. 14.5 Architecture. 14.6 ASIP validation. 14.7 Results. References. 15 Dynamically Reconfigurable Systems for Wireless Sensor Networks; H.Hinkelmann, P.Zipf, M.Glesner. 15.1 Introduction. 15.2 Motivation and Background. 15.3 Design of a Reconfigurable Function Unit . 15.4 Dynamic Reconfiguration. 15.5 General System Architecture. 15.6 Evaluation Results. 15.7 Prototyping of the Sensor Node System. 15.8 Generalisation of the Results. 15.9 Conclusion. References. 16 DynaCORE -- Dynamically Reconfigurable Coprocessor for Network Processors; C.Albrecht, J.Foag, R.Koch, E.Maehle, T.Pionteck. 16.1 Introduction. 16.2 Network Processors. 16.3 System Architecture. 16.4 Model. 16.5 Runtime Adaptive Network-on-Chip. 16.6 Reconfiguration Management. 16.7 Technical Aspects. 16.8 Evaluation. 16.9 Summary. References. 17 FlexPath NP- Flexible, Dynamically Reconfigurable Processing Paths in Network Processors; R.Ohlendorf, M.Meitinger, T.Wild, A.Herkersdorf. 17.1 Introduction. 17.2 FlexPath NP Concept . 17.3 Formal Analysis. 17.4 Simulative Exploration. 17.5 FPGA Demonstrator. 17.6 Conclusion. References. 18 AutoVision -- Reconfigurable Hardware Acceleration for Video-Based Driver Assistance; C.Claus, W.Stechele. 18.1 Introduction. 18.2 AutoVision architecture. 18.3 Fast Dynamic Partial Reconfiguration. 18.4 Results. 18.5 Performance of the Engines. 18.6 Conclusion and Outlook. References. 19 Procedures for securing ECC implementations against differential power analysis using reconfigurable architectures; M.Stottinger, F.Madlener, S.A.Huss. 19.1 Introduction. 19.2 Elliptic Curve Cryptography. 19.3 Side Channel Attacks. 19.4 Countermeasure through Reconfiguration. 19.5 DPA Experiments on Countermeasures. 19.6 Conclusion and Future Work. References. 20 Reconfigurable Controllers -- A Mechatronic Systems Approach; R.Kasper, S.Toscher. 20.1 Introduction. 20.2 Design Methodology . 20.3 Structure and Implementation. 20.4 Application. 20.5 Conclusion. References.