Digital Design and Modeling with VHDL and Synthesis

1.1 What Is VHDL?

1.2 VHDL Advantages.

1.3 What Is Logic Synthesis?.

1.4 New Design Methodology.

1.5 Book Overview.

1.6 Exercises.

Chapter 2: VHDL BASICS.

2.1 Lexial Elements, Separators, and Delimiters.

2.2 Identifiers.

2.3 Reserved Words.

2.4 Literals.

2.5 Package and Type.

2.6 Object Declaration.

2.7 Entity and Architecture.

2.8 Predefined Attributes.

2.9 Names and Operators.

2.10 Exercises.

Chapter 3: VHDL MODELLING CONCEPTS.

3.1 The Concept of the Signal.

3.2 Process Concurrency.

3.3 Delta Time.

3.4 Concurrent and Sequential Statements.

3.5 Process Activation by a Signal Event.

3.6 Signal-Valued and Signal-Related Attributes.

3.7 Exercises.

Chapter 4: SEQUENTIAL STATEMENTS.

4.1 Variable Assignment Statement.

4.2 Signal Assignment Statement.

4.3 If Statement.

4.4 Case Statement.

4.5 Loop Statement.

4.6 Next Statement.

4.7 Exit Statement.

4.8 Null Statement.

4.9 Procedure Call Statement.

4.10 Return Statement.

4.11 Assertion Statement.

4.12 Wait Statement.

4.13 Exercises.

Chapter 5: CONCURRENT STATEMENTS.

5.1 Process Statement.

5.2 Assertion Statement.

5.3 Concurrent Procedure Call Statement.

5.4 Conditional Signal Assignment Statement.

5.5 Selected Signal Assignment Statement.

5.6 Component Instantiation Statement.

5.7 Generate Statement.

5.8 Block Statement.

5.9 Exercises.

Chapter 6: SUBPROGRAMS AND PACKAGES.

6.1 Subprogram Declaration.

6.2 Subprogram Body.

6.3 Package Body.

6.4 Package Body.

6.5 Resolution Function.

6.6 Subprogram Overloading.

6.7 Subprogram Return Values and Types.

6.8 Type Casting and Type Qualification.

6.9 Exercises.

Chapter 7: DESIGN UNIT, LIBRARY, AND CONFIGURATION.

7.1 Architecture.

7.2 Entity Declaration.

7.3 Port Map and Generic Map.

7.4 Configuration.

7.5 Design Unit.

7.6 VHDL Library.

7.7 Block and Architecture Attributes.

7.8 Exercises.

Chapter 8: WRITING VHDL FOR SYNTHESIS.

8.1 General Guidelines of VHDL Synthesis.

8.2 Writing VHDL to Infer FlipFlops.

8.3 Writing VHDL to Infer Latches.

8.4 Writing VHDL to Infer Tristate Buffers.

8.5 Writing VHDL to Generate Combinational Circuits.

8.6 Putting Them Together.

8.7 Simulation versus Synthesis Differences.

8.8 Think About Hardware.

8.9 Use of Subprogram.

8.10 Synthesis Process.

8.11 Exercises.

Chapter 9: FINITE STATE MACHINES.

9.1 Finite State Machine Background.

9.2 Writing VHDL for a FSM.

9.3 FSM Initialization.

9.4 FSM Flipflop Output Signal.

9.5 FSM Synthesis.

9.6 Exercises.

Chapter 10: MORE ON BEHAVIOURAL MODELING.

10.1 File Types and File I/O.

10.2 ROM Model.

10.3 Bidirectional Pad Model.

10.4 Attribute Declaration and Attribute Specification.

10.5 Access and Record Type.

10.6 Guarded Block.

10.7 Guarded Signal and Null Waveform.

10.8 Disconnection Specification.

10.9 Writing Efficient VHDL Code.

10.10 Exercises.

Chapter 11: A DESIGN CASE AND TEST BENCH.

11.1 Design Description.

11.2 Writing VHDL Model.

11.3 Another Architecture.

11.4 A Test Bench.

11.5 Another Test Bench.

11.6 Synthesizing the Design.

11.7 Exercises.

Chapter 12: ALU DESIGN.

12.1 ALU Design Requirements.

12.2 Describing ALU with VHDL.

12.3 Improving the Design.

12.4 Simulate the Design with a Test Bench.

12.5 Exercises.

Chapter 13: A DESIGN PROJECT.

13.1 Design Requirements.

13.2 Functional VHDL Implementation.

13.3 VHDL Test Bench.

13.4 Synthesis and Layout.

13.5 Layout Backannotation and Verification.

13.6 VHDL Partitioning.

13.7 Exercises.

Chapter 14: VHDL'93.

14.1 More Regular Syntax.

14.2 Sequential Statements.

14.3 Concurrent Statements.

14.4 New Reserved Words.

14.5 Predifined STANDARD Package.

14.6 Attributes.

14.7 Direct Component Instantiation.

14.8 File and Text I/O.

14.9 Extended Identifier.

14.10 Exercises.

Appendix A: VHDL'87 QUICK REFERENCE.

Appendix B: DECLARATION PART TABLE.

Appendix C: VHDL'93 GRAMMER AND SYNTAX REFERENCE.

Index.