Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS

By: Brandon Noia, Krishnendu Chakrabarty

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Hardcover | 2 December 2013

At a Glance

Hardcover
264 Pages

Dimensions(cm)
24.13 x 16.51 x 1.91

Hardcover

$169.00

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This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

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