Introduction; Rudy Lauwereins, Jan Madsen Section 1: System Level Design Introduction: System Level Design: Past, Present and Future; Daniel D. Gajski Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems; P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, and P. Pop, DATE1998 EXPRESSION: A language for architecture exploration through compiler/simulator retargetability; A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, A. Nicolau, DATE1999 RTOS Modeling For System Level Design; A. Gerstlauer, H. Yu, D.D. Gajski, DATE2003 Context-aware performance analysis for efficient embedded system design; M. Jersak, R. Henia, R. Ernst, DATE2004 On Lock-Free Synchronization for Dynamic Embedded Real-Time Software; H. Cho, .B Ravindran, E.D. Jensen, DATE2006 What If You Could Design Tomorrow's System Today? N. Wingen, DATE2007 Section 2: Networks on Chip Introduction: Networks on Chip; Giovanni De Micheli A generic architecture for on-chip packet- switched interconnections; P. Guerrier, A. Greiner, DATE2000 Trade Offs In The Design Of A Router With Both Guaranteed And Best-Effort Services For Networks On Chip; E. Rijpkema, K.G.W. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander, DATE2003 Exploiting The Routing Flexibility For Energy-Performance Aware Mapping Of Regular Noc Architectures; J. Hu, R. Marculescu, DATE2003 xpipesCompiler: A tool for instantiating application specific Networks on Chip; A. Jalabert, S. Murali, L. Benini, G. De Micheli, DATE2004 Network traffic generator model for fast network-on-chip simulation; S. Mahadevan, F. Angiolini, M. Storoaard, R.G. Olsen, J. Sparsoe, J. Madsen, DATE2005 Section 3: Modeling, Simulation and Run-Time Management Introduction: Modeling, Simulation and Run-Time Management; Enrico Macii Dynamic power management for non-stationary service requests; E.Y. Chung, L. Benini, A. Bogiolo, G. De Micheli, DATE1999 Quantitative comparison of power management algorithms; Y. Lu, E. Chung, T. Simunic, L. Benini, G. De Micheli, DATE2000 Energy efficiency of the IEEE 802.15. 4 standard in dense wireless microsensor networks: modeling and improvement perspectives; B. Bougard, F. Catthoor, D.C. Daly, A. Chandrakasan, W. Dehaene, DATE2005 Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application; A. Singhee, R.A. Rutenbar, DATE2007 Compositional Specification of Behavioral Semantics; K. Chen, J. Sztipanovits and S. Neem, DATE2007 Section 4: Design technology for advanced digital systems in CMOS and beyond Introduction: Design technology for advanced digital systems in CMOS and beyond; Hugo De Man Address Bus Encoding Techniques for System-Level Power Optimization; L. Benini, G. De Micheli, E. Maccii, D. Sciuto, and C. Silvano, DATE1998 MOCSYN: Multiobjective core-based single-chip system synthesis; R.P. Dick, N.K. Jha, DATE1999 Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor; G. Quan and X. Hu, DATE2002 Synthesis and optimization of threshold logic networks with application to nanotechnologies; R. Zhang, P. Gupta, L. Zhong, N.K. Jha, DATE2004 Section 5: Physical design and validation Introduction: Physical Design and Validation; Jochen Jess Interconnect Tuning Strategies for High-Performance ICs; A.B. Kahng, S. Muddu, E. Sarto, and R. Sharma, DATE1998 Efficient Inductance Extraction Via Windowing; M.W. Beattie and L.T. Pileggi, DATE2001 Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits; Y.S. Dhillon, A.U. Diril, A. Chatterjee, DATE2005 A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology; C. Niclass, M. Sergio, E. Charbon, DATE2006 Section 6: Test and verification Introduction: Test and Verification; T.W. Williams and R. Kapur Cost reduction and evaluation of a temporary faults detecting technique; L. Anghel, M. Nicolaidis, DATE2000 An integrated system-on-chip test framework; E. Larsson, Z. Peng, DATE2001 Efficient Spectral Techniques For Sequential ATPG; A. Giani, S. Sheng and M.S. Hsiao, DATE2001 BerkMin: A Fast and Robust Sat-Solver; E. Goldberg and Y. Novikov, DATE2002 Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression; P. Gonciari, B. Al-Hashimi, and N. Nicolici, DATE2002 An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs; P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda, DATE2006 Appendix: Shortlist of most influential papers per year.
