Demystifying Chipmaking

By: Richard Yanda, Michael Heynes

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Paperback | 14 April 2005

At a Glance

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280 Pages

Dimensions(cm)
22.86 x 18.42 x 1.91

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This book takes the reader through the actual manufacturing process of making a typical chip, from start to finish, including a detailed discussion of each step, in plain language. The evolution of today's technology is added to the story, as seen through the eyes of the engineers who solved some of the problems. The authors are well suited to that discussion since they are three of those same engineers. They have a broad exposure to the industry and its technology that extends all the way back to Shockley Laboratories, the first semiconductor manufacturer in Silicon Valley.

The CMOS (Complementary Metal-Oxide-Semiconductor) process flow is the focus of the discussion and is covered in ten chapters. The vast majority of chips made today are fabricated using this general method. In order to ensure that all readers are comfortable with the vocabulary, the first chapter carefully and clearly introduces the science concepts found in later chapters. A chapter is devoted to pointing out the differences in other manufacturing methods, such as the gallium arsenide technology that produces chips for cell phones. In addition, a chapter describing the nature of the semiconductor industry from a business perspective is included.

"The entire process of making a chip is surprisingly easy to understand. The part of the story that defies belief is the tiny dimensions: the conducting wires and other structures on a chip are more than a hundred times thinner than a hair - and getting thinner with every new chip design."

Authors are actual engineers who have a broad range of exposure and experience with chip technology
Contains a unique chapter describing the nature of the semiconductor industry from a business perspective

Industry Reviews

"...a useful guide for engineers just entering the packaging sector of the semiconductor industry or for newly vetted engineering school grads." - Ron Iscoff, Editor, Chip Scale Review "Demystifying Chipmaking...will provide an interesting overview of the IC fabrication process while familiarizing you with the terminology." - Rick Nelson, Chief Editor, Test & Measurement World

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Electronic Devices & Materials Semi-Conductors & Super-Conductors Circuits & Components Computing & I.T.Computer Hardware Storage Media & Peripherals Energy Technology & Engineering Electrical Engineering

Technology in General Technical Design

Foreword	p. xi
Acknowledgments	p. xiii
About the Authors	p. xv
What's on the CD-ROM?	p. xvii
IC Fabrication Overview	p. 1
Introduction	p. 3
Integrated Circuits	p. 3
The Semiconductor Industry	p. 6
Support Technologies	p. 7
Crystal Growth and Wafer Preparation	p. 7
Contamination Control	p. 8
Circuit Design and Mask Making	p. 10
Process Diagnostics and Metrology	p. 12
Integrated Circuit Fabrication	p. 13
Layering	p. 13
Patterning	p. 18
Doping	p. 21
Process Control and In-line Monitoring	p. 22
Test and Assembly	p. 25
Electrical Tests	p. 25
Die Separation	p. 25
Die Attach and Wire Bonding	p. 25
Encapsulation	p. 26
Final Test	p. 26
Summary	p. 27
Support Technologies	p. 29
Introduction	p. 31
Contamination Control	p. 33
Why Control Contamination?	p. 33
Contamination Sources	p. 35
The Cleanroom	p. 36
Crystal Growth and Wafer Preparation	p. 41
Introduction	p. 41
Silicon Purification	p. 42
Czochralski Silicon Growth	p. 43
Shaping, Grinding, Cutting and Polishing	p. 46
Final Inspection and Shipping	p. 47
Circuit Design	p. 49
Introduction	p. 49
Product Definition and New Product Plan	p. 50
The Design Team	p. 53
The Design Process	p. 55
Design Verification and Tapeout	p. 57
Photomask and Reticle Preparation	p. 59
Introduction	p. 59
Reticle Substrate Preparation	p. 59
Pattern Transfer	p. 60
Inspection and Defect Repair	p. 61
Forming Wells	p. 63
Introduction	p. 65
Initial Oxidation	p. 71
Photolithography	p. 79
Introduction	p. 79
Coat (Spin)	p. 82
Exposure (Step)	p. 83
Develop	p. 84
After Develop Inspect (ADI)	p. 85
Ion Implantation	p. 87
Isolate Active Areas (Shallow Trench Isolation)	p. 93
Introduction to Shallow Trench Isolation	p. 95
Pad Oxide Growth	p. 99
Silicon Nitride Deposition	p. 101
Photolithography for Photo/Etch	p. 105
Hard Mask Formation Using Plasma Etch	p. 107
Hard Mask Overview	p. 107
Plasma Etch Overview	p. 109
Etch Chemistry: Silicon Dioxide and Silicon Nitride	p. 114
Form Trenches in Silicon with Plasma Etch	p. 119
Fill Trenches with Silicon Dioxide	p. 121
Chemical Mechanical Polishing (CMP) to Remove Excess Dioxide	p. 123
Wet Etch Removal of Silicon Nitride and Pad Oxide	p. 127
Building the Transistors	p. 129
Introduction	p. 131
Thin Film Formation	p. 137
Gate Dielectric Oxidation	p. 137
Polycrystalline Silicon (Poly) Deposition	p. 140
Nitride Cap Deposition	p. 142
Poly Gate Formation	p. 143
Photoresist Patterning	p. 143
Plasma Etch	p. 144
Source/Drain Formation	p. 147
Introduction	p. 147
Shallow Implant	p. 149
Spacer Formation	p. 149
High-Dose Implant	p. 151
Anneal	p. 151
Salicide Formation	p. 153
Sputter Cobalt	p. 155
RTP Reaction Forming Silicide	p. 155
Strip Residual Cobalt	p. 156
Anneal the Silicide	p. 156
First Level Metallization	p. 157
Introduction	p. 159
Nitride and Oxide Depositions	p. 163
Nitride Deposition	p. 163
Oxide Deposition	p. 164
CMP Planarization	p. 167
Photo/Etch for Contact Holes	p. 169
Contact Hole Photolithography	p. 169
Contact Etch	p. 170
Tungsten Plug Process	p. 173
Deposit Ti/TiN Barrier/Glue Layers	p. 173
Tungsten CVD	p. 174
Tungsten CMP	p. 176
Low-k Dielectric Process	p. 177
Deposit Low-k Dielectric Film	p. 177
Trench Photolithography and Etch	p. 180
Copper First Level Interconnection Process	p. 183
Ta/TaN Barrier Layer Deposition	p. 183
Sputter Copper (Cu)	p. 185
Electroplate Copper (Cu)	p. 185
Copper CMP	p. 186
Multilevel Metal Interconnects and Dual Damascene	p. 189
Introduction	p. 191
Deposit Barrier Layer and Intermetal Dielectric	p. 195
Dual Damascene Process	p. 197
Introduction	p. 197
Via Photo/Etch	p. 198
Trench Photo/Etch	p. 199
Deposit Barrier Layers	p. 200
Sputter Copper	p. 200
Electroplate Copper	p. 200
CMP to Remove Excess Copper	p. 201
Deposit SiC Barrier Layer	p. 202
Build Additional Layers	p. 202
Form Bonding Pads	p. 203
Final Passivation Process	p. 205
Deposit Final Passivation	p. 205
Photo/Etch for Bonding Pads	p. 205
Test and Assembly	p. 207
Introduction	p. 209
Wafer and Chip Testing	p. 211
In-line Parametric Test	p. 211
Wafer Sort (Probe)	p. 212
Final Functional Test	p. 213
Assembly and Packaging	p. 215
Die Separation	p. 215
Die Attach and Bond Pad Connection	p. 216
Encapsulation	p. 218
Science Overview	p. 219
Introduction	p. 221
Atoms and Molecules	p. 223
The Atom	p. 223
Molecules	p. 226
Organic Molecules	p. 227
Gases	p. 229
Facts about Gases	p. 229
Ions	p. 230
Plasma	p. 230
Free Radicals	p. 231
Excited States	p. 231
Chemistry	p. 233
Introduction	p. 233
Thin Film Deposition Chemistry	p. 233
Plasma Etch Chemistry	p. 235
Solids	p. 237
Conductors and Insulators	p. 237
Semiconductors	p. 238
pn Junctions	p. 239
Electricity, Electric and Magnetic Fields	p. 241
Electric Charges and Fields	p. 241
Electric Current	p. 242
Magnetic Field	p. 243
Plasma Etch Supplement to Chapter 4	p. 245
Plasma Etcher Theory	p. 247
Plasma Etch Process Requirements	p. 249
Bibliography	p. 251
Index	p. 253
Table of Contents provided by Ingram. All Rights Reserved.

Demystifying Chipmaking

At a Glance

Paperback

Industry Reviews

Shipping

How to return your order

Defective items

You Can Find This Book In

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