Data Converters for Wireless Standards

By: Chunlei Shi, Ismail Mohamed Mostafa

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Hardcover | 30 November 2001

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Hardcover
148 Pages

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23.5 x 15.88 x 1.27

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Wireless communication is witnessing tremendous growth with p- liferation of different standards covering wide, local and personal area networks (WAN, LAN and PAN). The trends call for designs that - low 1) smooth migration to future generations of wireless standards with higher data rates for multimedia applications, 2) convergence of wireless services allowing access to different standards from the same wireless device, 3) inter-continental roaming. This requires designs that work across multiple wireless standards, can easily be reused, achieve maximum hardware share at a minimum power consumption levels p- ticularly for mobile battery-operated devices. All this calls for higher levels of system integration of both the radio and the digital baseband parts. It also calls for radio design solutions with mixed signal strategies that take full advantage of technology sca- down by moving functions, such as channel select filtering, modulation and demodulation, to the digital domain. Central to achieving these goals is the design of data converters for these emerging standards in the context of technology and market trends.

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List of Figures	p. ix
List of Tables	p. xiii
Preface	p. xv
Introduction	p. 1
Background	p. 1
Motivation and Goals	p. 4
Organization	p. 5
Overview of Wireless Receiver Architectures	p. 7
Introduction	p. 7
Receiver Architecture	p. 7
Superheterodyne Architecture	p. 8
Zero-IF Architecture	p. 9
Low-IF Architecture	p. 10
Wideband IF Double Conversion Architecture	p. 10
Multi-standard Receiver Architecture	p. 12
Summary	p. 13
Low Power Adc Design	p. 15
Introduction	p. 15
Characterizations of ADC	p. 15
Review of ADC Architectures	p. 17
Flash ADC	p. 17
Interpolating and Folding ADC	p. 17
Two-Step ADC	p. 19
Oversampling ADC	p. 19
Pipeline ADC	p. 20
Overview of Pipeline ADC Designs	p. 21
Key Building Blocks	p. 21
Switched-Capacitor DAC and Residue Amplifier	p. 22
Sub-ADC	p. 22
Sample-and-Hold	p. 23
Digital Error Correction	p. 23
Design Considerations	p. 26
Size of Capacitors	p. 26
Capacitor Matching	p. 27
Amplifier Architecture	p. 28
Amplifier Requirements	p. 28
Error Tolerances	p. 31
Power Optimization Techniques	p. 32
Optimizing the Stage Resolution	p. 32
Dynamic Comparator	p. 33
Capacitor/Amplifier Scaling	p. 34
Dynamic Biasing	p. 34
Summary	p. 37
Prototype Design: Adc for Wlan(DSSS)/Wcdma	p. 39
Introduction	p. 39
Applications	p. 39
Architecture	p. 40
High-Speed OTA	p. 42
OTA Requirements	p. 42
OTA Topology	p. 43
DC Gain	p. 44
Gain-Bandwidth	p. 44
Slew Rate	p. 44
Thermal Noise	p. 45
CMFB	p. 45
Results	p. 45
Comparator	p. 46
Clock Generator	p. 47
Smart-Biasing Technique	p. 49
Prototype Implementation	p. 49
Performance of the Prototype ADC	p. 49
Summary	p. 50
Design Considerations of Low Voltage Adcs	p. 53
Introduction	p. 53
Challenges in Low Voltage ADC Design	p. 54
Low Voltage CMOS Switches	p. 56
Low-V[subscript T] Devices	p. 58
Clock Boosting	p. 59
Switched-Opamp	p. 60
A Modified Switched-opamp Technique	p. 62
Input Stage	p. 62
High Speed Design Techniques	p. 66
Summary	p. 68
Adc for Bluetooth/Wlan(Fhss)/Homerf	p. 71
Applications	p. 71
System Level Design	p. 73
A Switched-opamp MDAC	p. 74
Opamp Design	p. 75
DC Gain	p. 76
Frequency Response	p. 77
Slew Rate	p. 78
Noise	p. 79
Common-Mode Feedback (CMFB)	p. 80
Comparator Design	p. 81
Clock Generator	p. 83
Digital Correction Circuit	p. 84
Performance	p. 84
Summary	p. 86
High-Resolution Dac Design Techniques	p. 91
Review of DAC Architectures	p. 91
Current Steering DAC	p. 91
Switched-Capacitor DAC	p. 93
Resistor String DAC	p. 94
Intrinsic Matching of Resistor-String DAC	p. 94
Resistor Matching Model	p. 95
Design Techniques for Improved Resistor Matching	p. 97
Reducing Random Errors	p. 97
Reducing Gradient Errors	p. 99
Summary	p. 101
Control Dac for 3G (Umts) Transceivers	p. 103
Applications	p. 103
Design Specifications	p. 104
Architecture	p. 104
Design of Resistor Strings	p. 107
Class-AB Output Buffer	p. 108
Deglitching Circuit	p. 110
Performance of the Prototype DAC	p. 112
Summary	p. 114
Conclusion	p. 117
Index	p. 125
Table of Contents provided by Syndetics. All Rights Reserved.

Data Converters for Wireless Standards

At a Glance

Hardcover

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How to return your order

Defective items

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