| Introduction | p. 1 |
| Motivation and History | p. 1 |
| Intention of this Work | p. 3 |
| Further Recommended Literature | p. 3 |
| Organization of this Book | p. 5 |
| Basic Understanding of [Sigma][Delta] A/D Conversion | p. 7 |
| Basics of A/D Conversion | p. 7 |
| Sampling and Quantization | p. 7 |
| Quantizer White Noise Model | p. 10 |
| Performance Metrics | p. 11 |
| Frequency Domain Metrics | p. 12 |
| Noise and Power Metrics | p. 13 |
| Used Tools and Program Code | p. 15 |
| Performance of Nyquist Rate Converters | p. 16 |
| Performance of Oversampled Converters | p. 17 |
| Oversampled Noise-Shaping Converters: [Sigma][Delta] ADC | p. 18 |
| The First-Order [Sigma][Delta] Modulator | p. 20 |
| Pattern-Noise and Dithering in [Sigma][Delta] Modulators | p. 21 |
| Performance Increase in [Sigma][Delta] Modulators | p. 22 |
| High OSR [Sigma][Delta] Modulators | p. 23 |
| Higher Order [Sigma][Delta] Modulators | p. 23 |
| Multibit [Sigma][Delta] Modulators | p. 24 |
| Single-Loop, Single-Bit, Higher Order [Sigma][Delta] Modulators | p. 25 |
| Distributed Feedback Topology | p. 25 |
| Feed-Forward Topology | p. 27 |
| Local Feedback Loops | p. 28 |
| [Sigma][Delta] Modulator Loop Filter Stability and Scaling | p. 29 |
| Effective Quantizer Gain in [Sigma][Delta] Modulators | p. 32 |
| Multiloop, Cascaded [Sigma][Delta] Modulators | p. 33 |
| Specialized Architectures | p. 36 |
| Loop Filters with Bandpass Characteristic | p. 37 |
| Continuous-Time [Sigma][Delta] Modulators | p. 39 |
| CT [Sigma][Delta] Modulator Issues | p. 39 |
| Sampling Operation | p. 40 |
| Filter Realization | p. 41 |
| Quantizer Realization | p. 42 |
| Feedback Realization | p. 43 |
| DT/CT Modulators Trade-offs | p. 47 |
| DT-to-CT Conversion of [Sigma][Delta] Modulators | p. 47 |
| The Impulse-Invariant Transformation | p. 48 |
| Modified Z-Transform | p. 52 |
| Differences of the Two Transformations | p. 54 |
| DT-to-CT Conversion of Cascaded [Sigma][Delta] Modulators | p. 55 |
| Direct Filter Synthesis | p. 61 |
| STF and NTF in CT [Sigma][Delta] Modulators | p. 63 |
| Implicit Antialiasing Filter in CT [Sigma][Delta] Modulators | p. 65 |
| Implicit AAF of the CT Third-Order Modulator | p. 66 |
| Implicit AAF of the CT SOFO Modulator | p. 69 |
| Calculations with the CT Loop Filters | p. 71 |
| Alternatives for CT Filter Implementation | p. 71 |
| gmC-Integrator | p. 71 |
| LC-Resonator | p. 73 |
| Active gmC-Integrator | p. 74 |
| Current-mode Integrator | p. 75 |
| Log-Domain Integrator | p. 75 |
| Active RC-Integrator | p. 76 |
| Active MOSFET-C-Integrator | p. 77 |
| Conclusion on the Commonly Used CT Integrators | p. 77 |
| Classification of Non-Idealities in CT [Sigma][Delta] Modulators | p. 78 |
| Input Referred Errors | p. 81 |
| Organization of the Following Chapters | p. 83 |
| DAC Nonidealities in Continuous-Time [Sigma][Delta] Modulators | p. 85 |
| Feedback DAC Error Classification | p. 85 |
| Excess Loop Delay in Continuous-Time [Sigma][Delta] Modulators | p. 85 |
| Coefficient Mismatch through Excess Loop Delay | p. 86 |
| Increased Modulator Order through Excess Loop Delay | p. 87 |
| Alternative Approach to the Effect of Excess Loop Delay | p. 88 |
| Compensation for Excess Loop Delay in CT [Sigma][Delta] Modulators | p. 89 |
| Simulation Results on Excess Loop Delay | p. 92 |
| Extension to Other Architectures | p. 94 |
| Clock Jitter in Continuous-Time [Sigma][Delta] Modulators | p. 94 |
| Jitter Effects in CT [Sigma][Delta] Modulators | p. 94 |
| Calculation of the Jitter Influence for Rectangular Feedback | p. 96 |
| Reduction of Clock Jitter Influence Using Multibit DACs | p. 99 |
| Reduction of Clock Jitter Influence Using Shaped Feedback Waveform DACs | p. 100 |
| Further Possibilities for CT [Sigma][Delta] Modulators with Reduced Clock Jitter Sensitivity | p. 106 |
| CT Loop Filters Employing Shaped Feedback Waveforms | p. 107 |
| Trade-off for Reduced Clock Jitter Sensitivity | p. 108 |
| Discussion on the White Clock Jitter Model | p. 109 |
| Simulation Results on Clock Jitter | p. 110 |
| DAC Slew Rate Limitation | p. 113 |
| DAC Nonlinearity | p. 114 |
| Filter Nonidealities in Continuous-Time [Sigma][Delta] Modulators | p. 117 |
| Analytical Description | p. 117 |
| Analytical Description of the Nonideal CT Filter Behavior | p. 117 |
| Quantitative Impact of Nonideal CT Filter Behavior | p. 118 |
| Finite OpAmp Gain | p. 119 |
| Simulation Results | p. 121 |
| Integrator Gain or Time-Constant Error | p. 121 |
| Effective Quantizer Gain and Integrator Gain Errors | p. 122 |
| Single-Loop Modulators | p. 123 |
| Cascaded Modulators | p. 124 |
| Simulation Results | p. 125 |
| Compensation of Gain Errors in Single-Loop [Sigma][Delta] Modulators | p. 126 |
| Compensation of Gain Errors in Cascaded [Sigma][Delta] Modulators | p. 126 |
| Finite Amplifier Gain-Bandwidth Product | p. 128 |
| Basic Analytical Description of Finite GBW | p. 129 |
| Extended Model for Single-Loop Modulators | p. 131 |
| Compensation for Finite GBW-Induced Errors in CT [Sigma][Delta] Modulators | p. 134 |
| Influence on Different Feedback Implementations | p. 139 |
| Finite Amplifier Slew Rate | p. 141 |
| Slew Rate in CT [Sigma][Delta] Modulators | p. 141 |
| Influence of Different Feedback Waveforms and [Sigma][Delta] Architectures | p. 142 |
| Simulation Results | p. 143 |
| Other Integrator Nonidealities | p. 146 |
| Limited Output Swing | p. 146 |
| Circuit Noise | p. 147 |
| Integrator Nonlinearity | p. 150 |
| Quantizer Nonidealities in Continuous-Time [Sigma][Delta] Modulators | p. 155 |
| CT [Sigma][Delta] Modulator Design Examples | p. 157 |
| FOM Based Design Strategy for CT [Sigma][Delta] Modulators | p. 157 |
| Generic Figure of Merit Calculation | p. 158 |
| Single-Loop Architectures | p. 160 |
| Multibit Single-Loop Architectures | p. 161 |
| Cascaded Architectures | p. 162 |
| FOM Based Design Example: A 12-Bit 25 kHz [Sigma][Delta] Modulator | p. 163 |
| Expansion Features of the FOM Based Design Strategy | p. 164 |
| Low-Power Limits in Analog Circuits | p. 165 |
| Low-Power Limits in Noise-Dominated Circuits | p. 165 |
| Low-Power Limits in Noise-Dominated and Distortion-Dominated Circuits | p. 166 |
| Low-Power Limits in Matching-Dominated Circuits | p. 166 |
| Low-Power Limits in [Sigma][Delta] Modulators | p. 167 |
| Implementation Example I: A 12-Bit 25 kHz 1.5 V CT [Sigma][Delta] Modulator | p. 169 |
| Loop Filter Design | p. 170 |
| Circuit Blocks | p. 174 |
| Modulator Design | p. 178 |
| Measurements | p. 181 |
| Implementation Example II: A CT [Sigma][Delta] Modulator with SCR-Feedback | p. 185 |
| SCR-Feedback Implementation | p. 185 |
| SCR Time Constant and Loop Filter Scaling | p. 186 |
| Experimental Results | p. 188 |
| CT [Sigma][Delta] Modulator with SCR-I-Feedback | p. 189 |
| Implementation Example III: A 12-Bit 2 MHz 1 V CT [Sigma][Delta] Modulator | p. 191 |
| Modulator Architecture | p. 191 |
| Loop Filter | p. 192 |
| Circuit Implementation | p. 195 |
| Layout Consideration | p. 203 |
| Experimental Results | p. 203 |
| Implementation Example IV: A 2-1-1 Cascaded CT [Sigma][Delta] Modulator | p. 205 |
| Circuit Realization of the Cascaded Modulator | p. 207 |
| Measured Ideal Modulator Performance | p. 207 |
| Verification of the Digital Gain-Error Cancellation | p. 209 |
| Program Code | p. 213 |
| General Loop Filter Pole Transformation for the Exponential Feedback | p. 215 |
| On the CT Integrator, Sampling Frequency fs and the Amplifier GBW | p. 217 |
| References | p. 221 |
| Index | p. 239 |
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