| Preface | p. vii |
| Acknowledgements | p. xi |
| Table of Contents | p. xiii |
| List of Symbols and Abbreviations | p. xix |
| Introduction | p. 1 |
| The Explosive Growth of Mobile Communications | p. 1 |
| The Need for Cost Reduction | p. 3 |
| Cost Reduction through Integration | p. 3 |
| Research in the World: Transceivers from Past to Present | p. 5 |
| Research Work | p. 7 |
| The DCS-1800 Communication System | p. 11 |
| Introduction | p. 11 |
| Frequency Plan | p. 11 |
| Modulation Method | p. 12 |
| MSK Modulation | p. 12 |
| GMSK Modulation | p. 16 |
| Conclusion | p. 19 |
| Receiver Architecture and Specifications | p. 21 |
| Introduction | p. 21 |
| Cellular Receiver Architectures | p. 21 |
| The Super-Heterodyne Architecture | p. 22 |
| Structure | p. 22 |
| Properties | p. 22 |
| The Zero-IF and Low-IF Architecture | p. 24 |
| Structure | p. 24 |
| Properties | p. 26 |
| Other Architectures | p. 29 |
| A Low-IF Receive Path for a DCS-1800 Transceiver | p. 29 |
| From DCS Standard to Receiver Specifications | p. 31 |
| From Bit-error Rate to Signal-to-noise Ratio | p. 31 |
| Noise Figure | p. 33 |
| Image Rejection Ratio | p. 33 |
| LO Leakage | p. 36 |
| Intermodulation Performance | p. 37 |
| Phase Noise | p. 37 |
| Spurious Suppression | p. 39 |
| From Receiver Specifications to Circuit Specifications | p. 40 |
| The Low Noise Amplifier | p. 40 |
| Quadrature Mixers | p. 41 |
| VGA--Filter | p. 41 |
| A/D Converters | p. 42 |
| Overall Quadrature Accuracy | p. 43 |
| Specification Summary | p. 44 |
| DCS-1800 versus GSM-900 | p. 47 |
| Conclusion | p. 48 |
| Deep Submicron CMOS Transistors | p. 49 |
| Introduction | p. 49 |
| Hand Calculation Model | p. 50 |
| Transconductance and Transconductance Efficiency | p. 53 |
| Distortion and Intermodulation | p. 54 |
| Conclusion | p. 61 |
| RF CMOS Design for Analog Designers | p. 63 |
| Introduction | p. 63 |
| Impedance-, Power- and Noise Matching | p. 64 |
| Termination | p. 64 |
| Impedance Matching versus Power Matching | p. 65 |
| Noise Matching | p. 67 |
| MOS Power Matching by Inductive Source Degeneration | p. 68 |
| Matching Principle | p. 68 |
| Effective Transconductance and Power-to-Current Conversion | p. 68 |
| Analysis of the Power Flow | p. 70 |
| The Non-Quasi Static Effect | p. 72 |
| Origin of the Non-Quasi Static Effect | p. 72 |
| First Order Non-Quasi Static Model | p. 73 |
| Importance of the Non-Quasi Static Effect in the Low GHz Range | p. 75 |
| Optimum MOS Power Matching | p. 76 |
| Indirect Matching Principle | p. 76 |
| How Leaving Out the Matching Network M Affects the PCC | p. 77 |
| Fundamental Power Matching Limit | p. 78 |
| Noise Sources in MOS Devices | p. 81 |
| Classical Channel Thermal Noise | p. 81 |
| Non-Quasi Static Gate Noise Current | p. 83 |
| Exotic and Parasitic Noise Sources | p. 84 |
| Performing Advanced Noise Simulations in a Classical Simulator | p. 85 |
| The Noise Figure of an Input-Matched MOS Device | p. 86 |
| Noise Figure under Noise Matching Conditions | p. 87 |
| Noise Figure under Source Matching Constraints | p. 87 |
| Impact of the Source Matching Scheme on Noise Figure and PCC | p. 89 |
| Some Early Considerations on Noise Optimization | p. 92 |
| The IP[subscript 3] of an Input-Matched MOS Device | p. 94 |
| Impact of Feedback on Linearity | p. 95 |
| Case Study: The IP[subscript 3] of an Input-Matched MOS Device | p. 95 |
| Conclusions | p. 98 |
| Systematic CMOS LNA Design | p. 101 |
| Introduction | p. 101 |
| Narrow-band Low Noise Amplifier Topologies | p. 102 |
| Cascode Low Noise Amplifiers | p. 103 |
| Gain and Noise Figure | p. 105 |
| From PCC to Gain | p. 105 |
| Noise Figure | p. 106 |
| Impact of Input Capacitance on Matching, PCC and NF | p. 108 |
| Impact on Matching | p. 108 |
| Impact on PCC and Noise Figure | p. 111 |
| A Low-C[subscript p] Bondpad Structure with a High Q-factor | p. 113 |
| Impact of C[subscript gd] and M on Matching, PCC and NF | p. 114 |
| LNA Design Equations | p. 117 |
| The Design of the Cascode Device | p. 119 |
| Optimization of the Cascode Pole | p. 120 |
| Optimization of the Overall Noise Figure | p. 121 |
| Unwanted Side-effects Initiated by the Cascode | p. 122 |
| Systematic LNA Design: A Case Study | p. 123 |
| Target Specifications, Boundary Conditions and Constraints | p. 124 |
| Analysis of the Specification Dynamics | p. 125 |
| Contour-Based Sizing | p. 128 |
| Impact of the Source Resistance on Power Consumption | p. 131 |
| Fallacies and Pitfalls of LNA Noise Figure Dynamics | p. 133 |
| The Actual Importance of the Non-Quasi Static Gate Noise | p. 133 |
| The Tricky Relation between NF, g[subscript m] and Current Consumption | p. 135 |
| The First Pitfall: NF versus I[subscript DS] for a Fixed LNA (Fixed W/L) | p. 135 |
| The Second Pitfall: NF versus I[subscript DS] at a Fixed V[subscript GS] - V[subscript T] | p. 136 |
| Predicting the NF dynamics along an Arbitrary Trajectory | p. 137 |
| Impact of a Finite [Gamma] on LNA Performance | p. 138 |
| Impact of a Finite [Gamma] on PCC and NF | p. 138 |
| Main Conclusions | p. 140 |
| Mathematical Explanation | p. 142 |
| Impact of a Finite [Gamma] on IP[subscript 3] and Q[subscript in] | p. 145 |
| Intrinsically Unmatched Input Structures | p. 145 |
| Series Resonant Input Structure | p. 145 |
| Parallel Resonant Input Structure | p. 147 |
| Systematic LNA Design: The Case Study Revisited | p. 148 |
| From a 50 [Omega] Match to a 32 [Omega] Match | p. 148 |
| Direct Connection between the 50 [Omega] Source and the 32 [Omega] Input | p. 149 |
| Conclusion | p. 150 |
| A 0.25 [mu]m CMOS Receiver Prototype for DCS-1800 Cellular Communications | p. 153 |
| Introduction | p. 153 |
| Receiver Topology | p. 153 |
| Low Noise Amplifier | p. 153 |
| Down-converter with Active Inductor LO Interface | p. 155 |
| Design Considerations | p. 157 |
| Down-converter and Active Inductor LO Interface | p. 157 |
| Low Noise Amplifier | p. 159 |
| Realization | p. 160 |
| Experimental Results | p. 160 |
| Discussion | p. 163 |
| Conclusion | p. 165 |
| A 0.8 dB NF, ESD-protected CMOS LNA | p. 167 |
| Introduction | p. 167 |
| The GPS Frequency Plan in a Nutshell | p. 168 |
| GPS Power Levels and LNA Requirements | p. 168 |
| Topology | p. 170 |
| Design | p. 171 |
| Layout | p. 174 |
| Experimental Results | p. 176 |
| ESD Performance | p. 178 |
| Measured ESD Susceptibility | p. 178 |
| Expected ESD Performance with an On-chip Clamp | p. 178 |
| Discussion and Comparison with Existing CMOS LNAs | p. 178 |
| Conclusion | p. 181 |
| A 2V CMOS DCS-1800 Receiver Front-End | p. 183 |
| Introduction | p. 183 |
| Receiver Topology | p. 184 |
| The Down-Conversion Mixer and the Filter/VGA | p. 188 |
| Design Equations | p. 188 |
| Conversion Gain | p. 188 |
| Noise Figure | p. 189 |
| Linearity | p. 195 |
| DC offset | p. 195 |
| VGA input impedance | p. 196 |
| VGA stability | p. 197 |
| Design Procedure | p. 198 |
| The Low Noise Amplifier | p. 208 |
| Selection of the LNA Input Impedance | p. 208 |
| Optimization of the Coupling Capacitor | p. 208 |
| Design Trajectory | p. 210 |
| Practical Implementation | p. 210 |
| Layout | p. 213 |
| Experimental Results | p. 214 |
| Conclusion | p. 229 |
| Noise Figure of Receiver Systems | p. 231 |
| Sensitivity, Noise Factor and Noise Figure | p. 231 |
| Noise Figure of Receiver Building Blocks | p. 232 |
| Amplifiers | p. 232 |
| Mixers | p. 233 |
| Noise Figure of Receiver Systems | p. 235 |
| Single-Path Receivers | p. 235 |
| Quadrature Receivers | p. 236 |
| HD[subscript x] and IM[subscript x] Ratios based on Taylor Expansion of i[subscript DS] | p. 241 |
| Essentials of Two-port Noise Theory | p. 243 |
| Bibliography | p. 245 |
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