Computer-Aided Design and VLSI Device Development

Overview.- A : Numerical Simulation Systems.- 1. Numerical Simulation Systems.- 1.1 History of Numerical Simulation Systems.- 1.2 Implementation of a Numerical Simulation System.- 2. Process Simulation.- 2.1 Introduction.- 2.2 SUPREM: 1-D Process Simulator.- 2.3 SUPRA : 2-D Process Simulator.- 2.4 SOAP : 2-D Oxidation Simulator.- 3. Device Simulation.- 3.1 GEMINI : 2-D Poisson Solver.- 3.2 CADDET : 2-D 1-Carrier Device Simulator.- 3.3 PISCES-II : General-Shape 2-D 2-Carrier Device Simulator.- 4. Parasitic Elements Simulation.- 4.1 Introduction.- 4.2 SCAP2 : Two-Dimensional Poisson Equation Solver.- 4.3 FCAP3 : Three-Dimensional Poisson Equation Solver.- B : Applications and Case Studies.- 5. Methodology in Computer-Aided Design for Process and Device Development.- 5.1 Methodologies in Device Simulations.- 5.2 Outline of the case studies.- 6. SUPREM III Application.- 6.1 Introduction.- 6.2 Boron Implant Profiles.- 6.3 Thin Oxide Growth.- 6.4 Oxygen Enhanced Diffusion of Boron.- 6.5 Shallow Junctions.- 7. Simulation Techniques for Advanced Device Development.- 7.1 Device Physics for Process Development.- 7.2 CAD Tools for Simulation of Device Parameters.- 7.3 Methods of Generating Basic Device Parameters.- 7.4 Relationship between Device Characteristics and Process Parameters.- 8. Drain-Induced Barrier Lowering in Short Channel Transistors.- 9. A Study of LDD Device Structure Using 2-D Simulations.- 9.1 High Electric Field Problem in Submicron MOS Devices.- 9.2 LDD Device Study.- 9.3 Summary.- 10. The Surface Inversion Problem in Trench Isolated CMOS.- 10.1 Introduction to Trench Isolation in CMOS.- 10.2 Simulation Techniques.- 10.3 Analysis of the Inversion Problem.- 10.4 Summary of Simulation Results.- 10.5 Experimental Results.- 10.6 Summary.- 11. Development of Isolation Structures for Applications in VLSI.- 11.1 Introduction to Isolation Structures.- 11.2 Local Oxidation of Silicon (LOCOS).- 11.3 Modified LOCOS.- 11.4 Side Wall Masked Isolation (SWAMI).- 11.5 Summary.- 12. Transistor Design for Submicron CMOS Technology.- 12.1 Introduction to Submicron CMOS Technology.- 12.2 Development of the Submicron P-Channel MOSFET Using Simulations.- 12.3 N-Channel Transistor Simulations.- 12.4 Summary.- 13. A Systematic Study of Transistor Design Trade-offs.- 13.1 Introduction.- 13.2 P-Channel MOSFET with N- Pockets.- 13.3 The Sensitivity Matrix.- 13.4 Conclusions.- 14. MOSFET Scaling by CADDET.- 14.1 Introduction.- 14.2 Scaling of an Enhancement Mode MOSFET.- 14.3 Scaling of a Depletion Mode MOSFET.- 14.4 Conclusions.- 15. Examples of Parasitic Elements Simulation.- 15.1 Introduction.- 15.2 Two-Dimensional Parasitic Components Extraction.- 15.3 Three-Dimensional Parasitic Components Extraction.- Source Information of 2-D Programs.- Table of Symbols.- About the Authors.