Compilers and Operating Systems for Low Power

By: Luca Benini (Editor), Mahmut Kandemir (Editor), J. Ramanujam (Editor)

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Hardcover | 30 September 2003

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Hardcover
256 Pages

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Illustrated

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23.5 x 15.88 x 1.91

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Compilers and Operating Systems for Low Power focuses on both application-level compiler directed energy optimization and low-power operating systems. Chapters have been written exclusively for this volume by several of the leading researchers and application developers active in the field. The first six chapters focus on low energy operating systems, or more in general, energy-aware middleware services. The next five chapters are centered on compilation and code optimization. Finally, the last chapter takes a more general viewpoint on mobile computing. The material demonstrates the state-of-the-art work and proves that to obtain the best energy/performance characteristics, compilers, system software, and architecture must work together. The relationship between energy-aware middleware and wireless microsensors, mobile computing and other wireless applications are covered.

This work will be of interest to researchers in the areas of low-power computing, embedded systems, compiler optimizations, and operating systems.

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Non-Fiction Computing & I.T.Operating Systems Computer Programming & Software Development Compilers & Interpreters Computer Science Computer Architecture & Logic Design Engineering & Technology Energy Technology & Engineering Electrical Engineering

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Published: 22nd December 2012

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List of Figures	p. xi
List of Tables	p. xv
Contributing Authors	p. xvii
Preface	p. xix
Low Power Operating System for Heterogeneous Wireless Communication System	p. 1
Introduction	p. 2
Event-driven versus General-purpose OS	p. 3
PicoRadio II Protocol Design	p. 3
General-purpose Multi-tasking OS	p. 4
Event-driven OS	p. 8
Comparison Summary	p. 9
Low Power Reactive OS for Heterogeneous Architectures	p. 12
Event-driven Global Scheduler and Power Management	p. 12
TinyOS Limitations and Proposed Extensions	p. 14
Conclusion and Future Work	p. 15
References	p. 16
A Modified Dual-Priority Scheduling Algorithm for Hard Real-Time Systems to Improve Energy Savings	p. 17
Introduction	p. 17
Dual-Priority Scheduling	p. 19
Power-Low Modified Dual-Priority Scheduling	p. 21
Experimental Results	p. 28
Summary	p. 36
References	p. 36
Toward the Placement of Power Management Points in Real-Time Applications	p. 37
Introduction	p. 37
Model	p. 39
Sources of Overhead	p. 40
Computing the New Speed	p. 40
Setting the New Speed	p. 40
Speed Adjustment Schemes	p. 41
Proportional Dynamic Power Management	p. 41
Dynamic Greedy Power Management	p. 42
Evaluation of Power Management Schemes	p. 43
Optimal Number of PMPs	p. 44
Evaluation of the Analytical Model	p. 45
Conclusion	p. 48
Derivation of Formulas	p. 48
References	p. 51
Energy Characterization of Embedded Real-Time Operating Systems	p. 53
Introduction	p. 53
Related Work	p. 55
System Overview	p. 56
The Hardware Platform	p. 56
RTOS overview	p. 57
Characterization Strategy	p. 59
RTOS Characterization Results	p. 60
Kernel Services	p. 60
I/O Drivers	p. 62
Burstiness Test	p. 62
Clock Speed Test	p. 63
Resource Contention Test	p. 64
Application Example: RTOS vs Stand-alone	p. 65
Cache Related Effects in Thread Switching	p. 66
Summary of Findings	p. 66
Conclusions	p. 67
References	p. 72
Dynamic Cluster Reconfiguration for Power and Performance	p. 75
Motivation	p. 77
Cluster Configuration and Load Distribution	p. 78
Overview	p. 78
Implementations	p. 81
Methodology	p. 83
Experimental Results	p. 84
Related Work	p. 89
Conclusions	p. 91
References	p. 91
Energy Management of Virtual Memory on Diskless Devices	p. 95
Introduction	p. 96
Related Work	p. 97
Problem Formulation	p. 98
EEL[subscript RM] Prototype Compiler	p. 100
Phase 1 - Analysis	p. 100
Phase 2 - Code Generation	p. 101
Performance Model	p. 102
Example	p. 102
Implementation Issues	p. 103
Experiments	p. 105
Benchmark Characteristics	p. 106
Simulation Results	p. 107
Future Work	p. 110
Conclusion	p. 111
References	p. 111
Propagating Constants Past Software to Hardware Peripherals on Fixed-Application Embedded Systems	p. 115
Introduction	p. 116
Example	p. 119
Parameters in Cores	p. 120
Propagating Constants from Software to Hardware	p. 123
Experiments	p. 125
8255A Programmable Peripheral Interface	p. 126
8237A DMA Controller	p. 127
PC16550A UART	p. 128
Free-DCT-L Core	p. 128
Results	p. 131
Future Work	p. 133
Conclusions	p. 134
References	p. 134
Constructive Timing Violation for Improving Energy Efficiency	p. 137
Introduction	p. 137
Low Power via Fault-Tolerance	p. 139
Evaluation Methodology	p. 143
Simulation Results	p. 143
Related Work	p. 147
Conclusion and Future Work	p. 151
References	p. 151
Power Modeling and Reduction of VLIW Processors	p. 155
Introduction	p. 155
Cycle-Accurate VLIW Power Simulation	p. 156
IMPACT Architecture Framework	p. 156
Power Models	p. 157
PowerImpact	p. 158
Clock Ramping	p. 159
Clock Ramping with Hardware Prescan (CRHP)	p. 160
Clock Ramping with Compiler-based Prediction (CRCP)	p. 162
Basic CRCP Algorithm	p. 162
Reduction of Redundant Ramp-up Instructions	p. 164
Control Flow	p. 165
Load Instructions	p. 165
Experimental Results	p. 165
Conclusions and Discussion	p. 169
References	p. 170
Low-Power Design of Turbo Decoder with Exploration of Energy-Throughput Trade-off	p. 173
Introduction	p. 173
Data Transfer and Storage Exploration Methodology	p. 176
Global Data Flow and Loop Transformations	p. 178
Removal of Interleaver Memory	p. 178
Enabling Parallelism	p. 179
Storage Cycle Budget Distribution	p. 180
Memory Hierarchy Layer Assignment	p. 181
Data Restructuring	p. 182
Loop Transformations for Parallelization	p. 183
Loop Merging	p. 183
Loop Pipelining	p. 184
Partial Loop Unrolling	p. 184
Loop Transformation Results	p. 185
Storage Bandwidth Optimization	p. 185
Memory Organization	p. 186
Memory Organization Exploration	p. 186
Memory Organization Decision	p. 188
Conclusions	p. 190
References	p. 190
Static Analysis of Parameterized Loop Nests for Energy Efficient Use of Data Caches	p. 193
Introduction	p. 193
Energy and Line Size	p. 195
Background	p. 195
The Parameterized Loop Analysis	p. 197
Reduction to Single Reference Interference	p. 199
Interference and Reuse Trade-off	p. 200
STAMINA Implementation Results	p. 200
Swim from SPEC 2000	p. 201
Self Interference	p. 201
Tiling and Matrix Multiply	p. 202
Summary and Future Work	p. 203
References	p. 203
A Fresh Look at Low-Power Mobile Computing	p. 209
Introduction	p. 209
Architecture	p. 211
Handover and the Quantization of Computational Resources	p. 212
Standardization of Execution Environment's Parameters	p. 214
A Commercial Vision: Impact on Billing, Customer Loyalty and Churn	p. 215
Segmentation of Functionality: The XU-MS Split	p. 215
Use of Field-Programmable Hardware in the Mobile Station	p. 217
Special End-To-End Application Requirements	p. 217
Status and Research Vision	p. 218
References	p. 219
Index	p. 221
Table of Contents provided by Ingram. All Rights Reserved.

Compilers and Operating Systems for Low Power

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Hardcover

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