Closing the Gap Between ASIC & Custom

Tools and Techniques for High-Performance ASIC Design

By: David Chinnery, Kurt Keutzer

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Hardcover | 30 June 2002

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Hardcover
436 Pages

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23.5 x 16.51 x 2.54

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by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy's comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.

Industry Reviews

From the reviews:
"This book unveils the mystery behind the performance gap between ASIC and Custom design and shows how to close the gap with minimal design effort. A must read for every ASIC or ASSP designer."
(William J. Dally, Professor, Stanford University)
"Most IP core providers must provide high-performance designs within the constraints of an ASIC methodology. I'm optimistic that careful application of the techniques in this book will enable me to design embedded processors that do indeed close `the Gap Between ASIC and Custom'."
(Kees Vissers, Director of Architecture, Trimedia Technologies Inc.)
"This book provides a comprehensive explanation of why ASICs fall so far behind custom ICs in performance, and then shows how better tools, libraries and methodologies can narrow the gap. It's a must read for ASIC designers who want to boost performance - or custom designers who want to speed time to market with ASIC-like design methodologies."
(Richard Goering, EDA Editorial Director, EE Times)
"I've heard there is a price on the authors' heads. Power Users don't like people who give away their secrets."
(Gary Smith, Chief Analyst, Dataquest)
"This book reflects the best research to date on understanding the tradeoffs between full-custom intellectual property blocks and synthesized intellectual-property blocks - a topic we could only touch on in the Reuse Methodology Manual. It is required reading for anyone engaged in system-on-a-chip design."
(Michael Keating, author of the Reuse Methodology Manual, Vice-President, Synopsys)
"Solves one of life's little mysteries[...] It looks like it should become required reading for the IC innovators of this millennium."
(Neil Weste, author of Principles of CMOS VLSI Design, Cisco Systems, Inc.)

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computing & I.T.Computer Science Computer Architecture & Logic Design Energy Technology & Engineering Electrical Engineering

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Paperback

Published: 19th March 2013

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Preface	p. xi
List of trademarks	p. xv
Introduction and Overview of the Book	p. 1
Why are Custom Circuits so Much Faster?	p. 1
Who Should Care?	p. 1
Definitions: Asic, Custom, Etc.	p. 3
The 35,000 Foot View: Why is Custom Faster?	p. 4
Microarchitecture	p. 9
Timing Overhead: Clock Tree Design and Registers	p. 12
Logic Style	p. 15
Logic Design	p. 17
Cell Design and Wire Sizing	p. 18
Layout: Floorplanning and Placement to Manage Wires	p. 20
Process Variation and Improvement	p. 22
Summary and Conclusions	p. 26
What's not in the Book	p. 28
Organization of the Rest of the Book	p. 28
Contributing Factors
Improving Performance through Microarchitecture	p. 33
Examples of Microarchitectural Techniques to Increase Speed	p. 34
Memory Access Time and the Clock Period	p. 44
Speedup from Pipelining	p. 45
Reducing the Timing Overhead	p. 57
Characteristics of Synchronous Sequential Logic	p. 58
Example Where Latches are Faster	p. 77
Optimal Latch Positions with Two Clock Phases	p. 81
Example Where Latches are Slower	p. 83
Pipeline Delay with Latches Vs. Pipeline Delay with Flip-Flops	p. 87
Custom Versus Asic Timing Overhead	p. 90
High-Speed Logic, Circuits, Libraries and Layout	p. 101
Introduction	p. 101
Technology Independent Metrics	p. 102
Performance Penalties in Asic Designs from Logic Style, Logic Design, Cell Design, and Layout	p. 108
Comp Arison of Asic and Custom Cell Areas	p. 129
Energy Tradeoffs Between Asic Cells and Custom Cells	p. 133
Future Trends	p. 138
Summary	p. 139
Finding Peak Performance in a Process	p. 145
Process and Operating Conditions	p. 146
Chip Speed Variation Due to Statistical Process Variation	p. 155
Continuous Process Improvement	p. 157
Speed Differences Due to Alternative Process Implementations	p. 159
Process Technology for Asics	p. 161
Potential Improvements for Asics	p. 164
Design Techniques
Physical Prototyping Plans for High Performance	p. 169
Introduction	p. 169
Floorplanning	p. 170
Physical Prototyping	p. 172
Techniques in Physical Prototyping	p. 180
Conclusions	p. 185
Automatic Replacement of Flip-Flops by Latches in ASICs	p. 187
Introduction	p. 187
Theory	p. 191
Algorithm	p. 199
Results	p. 203
Conclusion	p. 207
Useful-Skew Clock Synthesis Boosts ASIC Performance	p. 209
Introduction	p. 209
Is Clock Skew Really Global?	p. 210
Permissible Range Skew Constraints	p. 211
Why Clock Skew May be Useful	p. 213
Useful Skew Design Methodology	p. 216
Useful Skew Case Study	p. 218
Clock and Logic Co-Design	p. 220
Simultaneous clock Skew Optimization and Gate Sizing	p. 220
Conclusion	p. 221
Faster and Lower Power Cell-Based Designs with Transistor-Level Cell Sizing	p. 225
Introduction	p. 225
Optimized Cells for Better Power and Performance	p. 226
PPO Flow	p. 228
PPO Examples	p. 235
Flow Challenges and Adoption	p. 238
Conclusions	p. 239
Design Optimization with Automated Flex-Cell Creation	p. 241
Flex-Cell Based Optimization-Overview	p. 244
Minimizing the Number of New Flex-Cells Created	p. 249
Cell Layout Synthesis in Flex-Cell Based Optimization	p. 254
Greater Performance Through Better Characterization	p. 255
Physical Design and Flex-Cell Based Optimization	p. 259
Case Studies with Results	p. 261
Conclusions	p. 266
Exploiting Structure and Managing Wires to Increase Density and Performance	p. 269
Inherent Design Structure	p. 269
Successive Custom Techniques for Exploiting Structure	p. 271
Future Directions	p. 285
Summary	p. 285
Semi-Custom Methods in a High-Performance Microprocessor Design	p. 289
Introduction	p. 289
Custom Processor Design	p. 290
Semi-Custom Deisgn Flow	p. 291
Design Example - 24 Bit Adder	p. 297
Overall Impact on Chip Design	p. 300
Controlling Uncertainty in High Frequency Designs	p. 305
Introduction	p. 305
Frequency Terminology	p. 305
Uncertainty Defined	p. 306
Why Uncertainty Reduces the Maximum Possible Frequency	p. 309
Practical Example of Tool Uncertainty	p. 312
Focused Methodology Development	p. 314
Methods for Removing Paths from the Uncertainty Window	p. 315
The Uncertainty Lifecycle	p. 317
Conclusion	p. 321
Increasing Circuit Performance through Statistical Design Techniques	p. 323
Process Variability and its Impact on Timing	p. 324
Increasing Performance Through Probabilistic Timing Modeling	p. 329
Increasing Performance Through Design for Manufacturability Techniques	p. 334
Accounting for Impact of Gate Length Variation on Circuit Performance: A Case Study	p. 338
Conclusion	p. 342
Design Examples
Achieving 550MHz in a Standard Cell ASIC Methodology	p. 345
Introduction	p. 345
A Design Bridging the Speed Gap Between ASIC and Custom	p. 346
Microarchitecture: Pipelining and Logic Design	p. 348
Register Design	p. 352
Clock Tree Insertion and Clock Distribution	p. 356
Custom Logic Versus Synthesis	p. 357
Reducing Uncertainty	p. 358
Summary and Conclusions	p. 358
The iCORE 520MHz Synthesizable CPU Core	p. 361
Introduction	p. 361
Optimizing the Microarchitecture	p. 363
Optimizing the Implementation	p. 375
Physical Design Strategy	p. 378
Results	p. 379
Conclusions	p. 380
Creating Synthesizable ARM Processors with Near Custom Performance	p. 383
Introduction	p. 383
The ARM7TDMI Embedded Processor	p. 384
The Need for a Synthesizable Design	p. 391
The ARM7S Project	p. 392
The ARM9S Project	p. 400
The ARM9S Derivative Processor Cores	p. 403
Next Generation Core Developments	p. 406
Table of Contents provided by Syndetics. All Rights Reserved.

Closing the Gap Between ASIC & Custom

Tools and Techniques for High-Performance ASIC Design

At a Glance

Hardcover

Industry Reviews

Shipping

How to return your order

Defective items

You Can Find This Book In

Other Editions and Formats

Paperback

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