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Automatic Layout Modification

Including Design Reuse of the Alpha CPU in 0.13 Micron Soi Technology

By: Michael Reinhardt

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Hardcover | 30 June 2002

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244 Pages

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23.5 x 15.88 x 1.91

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According to the Semiconductor Industry Association's 1999 International Technology Roadmap for Semiconductors, by the year 2008 the integration of more than 500 million transistors will be possible on a single chip. Integrating transistors on silicon will depend increasingly on design reuse. Design reuse techniques have become the subject of books, conferences, and podium discussions, with most focusing on higher-level abstraction like RTL descriptions, which can be synthesized. Design reuse is often seen as an add-on to normal design activity, or a special design task that is not an integrated part of the existing design flow. This may all be true for the ASIC world, but not for high-speed, high-performance microprocessors. In the field of high-speed microprocessors, design reuse is an integrated part of the design flow. The method of choice in this demanding field was, and is always, physical design reuse at the layout level. In the past, the practical implementations of this method were linear shrinks and the lambda approach. With the scaling of process technology down to 0.8 micron and below, this approach lost steam and became inefficient. The only viable solution is a method called Automatic Layout Modification (ALM), which combines compaction, mask manipulation, and correction with powerful capabilities. This text is a comprehensive reference work on the subject.

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Automatic Control Engineering Energy Technology & Engineering Electrical Engineering Computing & I.T.Graphical & Digital Media Applications Computer Science Electronic Devices & Materials

Microprocessors

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Paperback

Published: 17th March 2013

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Foreword	p. xiii
Acknowledgments	p. xv
Introduction to IC Physical Design Reuse	p. 1
Purpose of This Book	p. 3
Structure of This Book	p. 3
History of Physical Design Reuse	p. 4
Physical Design Reuse in the SOC Era: Luxury or Necessity?	p. 7
Increasing Design Complexity	p. 8
The Design Automation Gap and Physical Challenges of UDSM Technology	p. 9
Demand for Shorter Design Time	p. 11
Early Access to the Latest Process Technology	p. 12
Shortage of Qualified Engineering Resources	p. 13
Design Cost: A Critical Factor in SOC Design	p. 14
Boosting Design Capabilities with Automatic Layout Modification Technology	p. 15
Speeding Up Initial Layout Creation	p. 15
Compacting layouts	p. 18
Automatic design-rule correction	p. 18
Device size adjustment	p. 20
Layout Migration Methods	p. 22
Re-layout of an entire circuit	p. 22
Linear shrink method	p. 23
Flexible layout conversion using Automatic Layout Modification Technology	p. 25
Customizing Layout Designs	p. 26
High-voltage or low-voltage?	p. 26
Adjusting circuit speed	p. 28
Low-power applications	p. 28
Adjustments for different process options	p. 30
Customizing cell libraries	p. 30
Achieving Timing Closure	p. 30
The timing challenge in DSM technologies	p. 31
Detecting timing problems inside a circuit	p. 34
Changing transistor sizes	p. 38
Modifying wire capacitance and resistance	p. 39
Clock optimization	p. 40
Solving Signal Integrity Problems in DSM Circuits	p. 40
Reducing noise	p. 40
Reducing crosstalk	p. 42
Design Optimization	p. 43
Timing optimization	p. 43
Power optimization	p. 43
Yield optimization	p. 44
Electro-migration	p. 45
Optical Mask Enhancement	p. 46
Optical proximity correction	p. 46
OPC avoidance	p. 48
Phase shift mask correction	p. 49
Characteristics and Functionalities of an Automatic Layout Modification Tool Suite	p. 51
Migrating the Electrical Characteristics of a Layout	p. 51
Signal-Specific Layout Manipulation Support	p. 55
Solving signal integrity problems	p. 55
Signal-specific wire sizing and spacing of critical signals	p. 56
Shielding and moving signals to separate metal levels	p. 57
Ensuring Layout Quality Throughout an Automatic Layout Modification	p. 59
Controlling the number of notches and jogs	p. 59
Handling orthogonal and non-orthogonal structures	p. 60
Improving connectivity	p. 62
Improving latch-up characteristics	p. 63
Improving the power grid	p. 64
Applying "recommended rules"	p. 66
Modifying Libraries Automatically	p. 68
Processing an entire library	p. 69
Supporting multiple grids	p. 69
Controlling power bus width and cell height	p. 70
Creating pick-up ports	p. 71
Checking and evaluating an entire library	p. 71
Modifying Large Databases	p. 72
Using distributed processing	p. 72
Modifying hierarchical layouts	p. 73
Using a hierarchy analysis and extraction tool	p. 74
Defining and Entering Design Rules	p. 74
Preparing and Analyzing Layouts	p. 74
Extracting Netlists	p. 75
Integrating Automatic Layout Modification Technology and Physical Design Reuse into Existing Design Flows	p. 77
The Typical ASIC Design Flow	p. 78
Adding Physical Design Reuse Capability to the ASIC Flow	p. 81
The Layout Conversion Flow	p. 82
The geometrical process relationship	p. 83
The electrical process relationship	p. 84
Applying Automatic Layout Modification Technology and Design Reuse Techniques to New Designs	p. 86
An Incremental Approach to Timing and Signal Integrity Design Improvements	p. 87
Optimizing Power Consumption and Yield Using Automatic Layout Modification Techniques	p. 88
Applying Physical Design Reuse to Different Design Types with Automatic Layout Modification Technology	p. 91
Digital Macro Blocks	p. 91
Standard cell blocks	p. 92
Digital full-custom designs	p. 94
Timing closure and Physical Design Reuse	p. 95
Early process access and decreased ramp-up time	p. 95
Need for design portability	p. 96
Integrating external IP into SOC designs	p. 97
Moving to place & route-based design flows	p. 97
Structured full-custom designs	p. 98
Datapath designs	p. 98
Memory	p. 99
Analog Circuits	p. 99
Standard Cell Libraries	p. 100
Physical Compilers	p. 102
Layout Guidelines for Physical Design Reuse and Automatic Layout Modification	p. 103
General Layout Design Guidelines	p. 103
Laying out polygon structures	p. 103
Positioning text	p. 104
Using diamond- and octagonal-shaped structures	p. 104
Using 45-degree transistors	p. 105
Maintaining one-to-one device and cell relationships	p. 106
Separating analog structures	p. 107
Modifying Hierarchical Layouts	p. 108
Fulfilling the abutting cells requirement	p. 108
Enforcing array-type base structures	p. 110
Maintaining rotated and mirrored cells	p. 110
Handling deadlock situations	p. 111
Handling naming and text conventions	p. 111
Matching of netlist and layout hierarchies	p. 112
Partitioning Layouts (Floorplanning) for Physical Design Reuse	p. 112
Reusing standard cell blocks	p. 113
Reusing full-custom design blocks	p. 114
Reusing mixed-signal designs	p. 114
Designing Layouts for Portability	p. 114
Using orthogonal versus non-orthogonal structures	p. 114
Using local interconnect	p. 115
Handling butted tap contacts and shared contacts	p. 116
Using buried contacts	p. 117
Laying Out Analog Structures	p. 117
Guide to Physical Design Reuse Tools: Uses and Functions	p. 119
Design Analysis Tools	p. 119
Electrical (parasitic) extraction tools	p. 120
Extraction methods	p. 120
Determining critical signals	p. 122
Critical signal extraction tools	p. 123
Static and dynamic timing analysis tools	p. 123
Critical signal RC delay comparison tools	p. 124
Noise, crosstalk, and signal integrity analysis tools	p. 125
Static and dynamic power analysis tools	p. 125
Design Optimization	p. 126
Timing optimization tools	p. 126
Power optimization tools	p. 127
Layout Modification	p. 128
Place & route tools	p. 128
Layout editing tools	p. 129
Compaction tools	p. 130
Automatic layout modification tools	p. 134
Design Verification	p. 131
LVS and DRC tools	p. 131
Timing verification tools	p. 132
General Layout Modification Design Flow as Applied to the Alpha CPU Migration	p. 133
General Layout Modification Design Flow	p. 133
Alpha Microprocessor Project Overview	p. 134
Migration methodology	p. 135
EV7 Microprocessor Core Database Assessment	p. 136
The Challenge: Layout Correction	p. 136
Basic design-rule violations	p. 137
Poly endcap	p. 137
Poly spacing	p. 137
Gate spacing	p. 138
Local interconnect spacing	p. 138
Contact spacing	p. 138
Contact/local interconnect overhang	p. 139
Generating a high-threshold voltage mask	p. 140
Impact of hierarchy on layout correction	p. 141
No metal modification allowed	p. 142
Maintaining the same number of leaf cells	p. 142
Exclusion of certain cells and "don't-touch" areas	p. 142
The Alpha Layout Modification Flow	p. 142
Phase 1: Hierarchical Linear Shrink and Lambda Approach	p. 143
Phase 2: Cleaning up the Database	p. 144
Removing redundant polygons	p. 144
Optimizing the hierarchy	p. 145
Removing unconnected diffusion and local interconnect	p. 146
Phase 3: Analyzing the Database	p. 146
Extracting hierarchy information	p. 146
Merging macro blocks	p. 147
Phase 4: Layout Correction Flow	p. 147
Preparing the layout for correction	p. 148
Device extraction	p. 148
Netlist extraction	p. 148
Extracting specific layout situations	p. 149
Merging polygons	p. 150
Combining polygons from different cell levels	p. 150
Enlarging endcaps	p. 151
Enlarging end-of-line rules for LI over-contacts	p. 152
Combining cross-shaped LI on same node	p. 152
Creating pseudo-contacts for LI/poly and LI/diffusion	p. 152
Measuring design sizes	p. 153
Checking and correction	p. 153
Checking the design	p. 153
Correcting the design	p. 154
Phase 5: Reconstructing the Layout	p. 155
External verification	p. 155
Project Results	p. 155
Memory and CPU time requirements	p. 155
Amount of error reduction	p. 157
Aspects of Memory Conversion Projects	p. 159
Typical Memory Structure	p. 160
Special Requirements of Memory Conversion	p. 161
Handling memory bit cell	p. 161
Pitch matching leaf cells	p. 162
Different sizing of different memory areas	p. 164
Considering all possible memory configurations	p. 164
Maintaining layout hierarchy for verification	p. 164
Special device sizing for drivers and sense amplifiers	p. 165
Supporting a special grid for memory ports	p. 165
Typical memory conversion flow	p. 166
Creating typical configurations	p. 166
Reducing overall complexity	p. 167
Analyzing memory configurations	p. 168
Calculating device sizes	p. 168
Reduction or shrink factor analysis	p. 168
Conversion and correction flow	p. 169
Reconstructing the memory	p. 170
Creating phantoms for place & route	p. 170
Aspects of Library Conversion Projects	p. 171
Typical Standard Cell Structures	p. 171
Special Standard Cell Library Conversion Requirements	p. 174
Considering all possible configurations	p. 175
Special device sizing of output drivers	p. 176
Supporting a special grid for ports	p. 177
Standard Cell Library Conversion Flow	p. 177
Enhancing the library	p. 177
Calculating device sizing and power bus width	p. 177
Adjusting the physical layout	p. 178
Verifying the physical layout	p. 179
Characterizing library cells	p. 179
Updating views for EDA tools	p. 180
Converting I/O Cells	p. 180
I/O cell structures	p. 180
Converting ESD and bonding pad structures	p. 181
Converting the logic parts of I/O cells	p. 182
Special-Purpose Libraries	p. 182
Gate Array Libraries	p. 182
Key Algorithms Used for Automatic Layout Modification Technology	p. 183
Mask Operations	p. 184
Logical mask operations	p. 185
Selection operations	p. 186
Sizing operations	p. 187
Layer operations	p. 188
Check functions	p. 190
Implementation options for mask operations	p. 190
Types of Compaction Algorithms	p. 191
Symbolic compaction--polygon compaction	p. 191
One-dimensional--two-dimensional	p. 192
Orthogonal--non-orthogonal structures	p. 194
Flat compaction--hierarchical compaction	p. 194
Compaction Algorithms in ALM	p. 195
Shear line or virtual grid compaction	p. 195
Constraint graph compaction	p. 197
Iterative edge compaction	p. 198
Compaction Algorithms for Full Hierarchical Designs	p. 201
Limitations of Compaction	p. 204
Layout Correction Algorithms	p. 205
Mask operations for design-rule correction	p. 206
Grid snapping error correction after a linear shrink	p. 207
Correcting hierarchical layouts	p. 207
Bibliography	p. 211
Glossary	p. 215
Index	p. 219
Table of Contents provided by Syndetics. All Rights Reserved.

Automatic Layout Modification

Including Design Reuse of the Alpha CPU in 0.13 Micron Soi Technology

At a Glance

Hardcover

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How to return your order

Defective items

You Can Find This Book In

Other Editions and Formats

Paperback

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