Asynchronous Pulse Logic

By: Mika M. Nystrom, Alain Martin

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Hardcover | 31 May 2002

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Hardcover
236 Pages

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23.5 x 15.88 x 1.91

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Asynchronous Pulse Logic is a comprehensive analysis of a newly developed asynchronous circuit family. The book covers circuit theory, practical circuits, design tools and an example of the design of a simple asynchronous microprocessor using the circuit family.
Asynchronous Pulse Logic will be of interest to industrial and academic researcher working on high-speed VLSI systems. Graduate students will find this useful reference for computer-aided design of asynchronous or related VLSI systems.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Energy Technology & Engineering Electrical Engineering Computing & I.T.Computer Science Systems Analysis & Design

List of Figures	p. xi
Preface	p. xv
Acknowledgments	p. xxi
First Author's Personal Thanks	p. xxiii
Preliminaries	p. 1
High-speed CMOS-circuits	p. 1
Asynchronous protocols and delay-insensitive codes	p. 3
Production rules	p. 4
The MiniMIPS processor	p. 4
Commonly used abbreviations	p. 6
Asynchronous-Pulse-Logic Basics	p. 7
Road map of this chapter	p. 9
The pulse repeater	p. 10
Timing constraints in the pulse repeater	p. 11
Simulating the pulse repeater	p. 11
The synchronous digital model	p. 18
Asymmetric pulse-repeaters	p. 20
Formal model of pulse repeater	p. 21
Basic definitions	p. 21
Handling the practical simulations	p. 22
Expanding the model	p. 24
Using the extended model	p. 26
Noise margins	p. 28
Differential-equations treatment of pulse repeater	p. 29
Input behavior of pulse repeater	p. 30
Generalizations and restrictions	p. 34
Computing with Pulses	p. 37
A simple logic example	p. 38
Pulse-handshake duty-cycle	p. 42
Single-track-handshake interfaces	p. 45
Timing constraints and timing "assumptions"	p. 46
Minimum cycle-transition-counts	p. 47
Solutions to transition-count problem	p. 48
The APL design-style in short	p. 48
A Single-Track Asynchronous-Pulse-Logic Family: I. Basic Circuits	p. 51
Preliminaries	p. 51
Transition counting in pipelined asynchronous circuits	p. 52
Transition-count choices in pulsed circuits	p. 53
Execution model	p. 56
Capabilities of the STAPL family	p. 56
Design philosophy	p. 58
The basic template	p. 58
Bit generator	p. 59
Bit bucket	p. 63
Left-right buffer	p. 66
Summary of properties of the simple circuits	p. 71
A Single-Track Asynchronous-Pulse-Logic Family: II. Advanced Circuits	p. 73
Multiple input and output channels	p. 73
Naive implementation	p. 74
Double triggering of logic block in the naive design	p. 75
Solution	p. 76
Timing assumptions	p. 77
General logic computations	p. 77
Inputs whose values are not used	p. 78
Conditional communications	p. 81
The same program can be expressed in several ways	p. 83
Simple techniques for sends	p. 83
General techniques for conditional communications	p. 84
Storing state	p. 89
The general state-storing problem	p. 89
Implementing state variables	p. 90
Compiling the state bit	p. 92
Special circuits	p. 95
Arbitration	p. 96
Four-phase converters	p. 99
Resetting STAPL circuits	p. 100
Previously used resetting schemes	p. 101
An example	p. 104
Generating initial tokens	p. 104
How our circuits relate to the design philosophy	p. 105
Noise	p. 106
External noise-sources	p. 106
Charge sharing	p. 107
Crosstalk	p. 107
Design inaccuracies	p. 109
Automatic Generation of Asynchronous-Pulse-Logic Circuits	p. 111
Straightforwardly compiling from a higher-level specification	p. 111
An alternative compilation method	p. 113
What we compile	p. 113
The PL1 language	p. 114
Channels or shared variables?	p. 115
Simple description of the PL1 language	p. 115
An example: the replicator	p. 117
Compiling PL1	p. 118
PL1-compiler front-end	p. 120
Determinism conditions	p. 120
Data encoding	p. 122
PL1-compiler back-end	p. 124
Slack	p. 125
Logic simplification	p. 127
Code generation	p. 129
A Design Example: The Spam Microprocessor	p. 133
The SPAM architecture	p. 133
SPAM implementation	p. 134
Decomposition	p. 134
Arbitrated branch-delay	p. 136
Byte skewing	p. 137
Design examples	p. 140
The PCUNIT	p. 140
The REGFILE	p. 151
Performance measurements on the SPAM implementation	p. 158
Straightline program	p. 158
Computing Fibonacci numbers	p. 160
Energy measurements	p. 162
Summary of SPAM implementation's performance	p. 163
Comparison with QDI	p. 163
Related Work	p. 167
Theory	p. 167
STAPL circuit family	p. 167
PL1 language	p. 169
SPAM microprocessor	p. 170
Lessons Learned	p. 171
Conclusion	p. 172
Appendices	p. 173
PL1 Report	p. 173
Scope	p. 173
Structure of PL1	p. 173
Syntax elements	p. 174
Keywords	p. 174
Comments	p. 174
Numericals	p. 174
Identifiers	p. 174
Reserved special operators	p. 174
Expression operators	p. 174
Expression syntax	p. 175
Actions	p. 175
PL1 process description	p. 176
Declarations	p. 176
Communication statement	p. 176
Process communication-block	p. 176
Semantics	p. 178
Expression semantics	p. 178
Action semantics	p. 180
Execution semantics	p. 180
Invariants	p. 181
Semantics in terms of CHP	p. 181
Slack elasticity	p. 183
Examples	p. 184
SPAM Processor Architecture Definition	p. 187
SPAM overview	p. 187
SPAM instruction format	p. 187
SPAM instruction semantics	p. 189
Operand generation	p. 189
Operation definitions	p. 189
Assembly-language conventions	p. 191
The SPAM assembly format	p. 191
Proof that Definition 2.2 Defines a Partial Order	p. 193
Remark on Continuity	p. 194
Table of Contents provided by Syndetics. All Rights Reserved.

Asynchronous Pulse Logic

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Hardcover

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