Analog Circuits and Signal Processing

Dedication. Preface. Acknowledgements. List of Abbreviations. 1 Introduction. 1.1 Low-Voltage High-Speed Analog-to-Digital Conversion. 1.2 Applications of High-Speed ADCs. 1.3 Deep-Submicron CMOS ADCs Designs. 1.4 Research Objectives and Design Challenges. 1.5 References. 2 Challenges in Low-Voltage Circuit Designs. 2.1 Introduction. 2.2 The Impact of CMOS Technology Scaling. 2.3 Design Challenges - Intrinsic Performance Degradation. 2.4 Circuit Level Design Challenges -- Opamps. 2.5 Circuit Level Design Challenges -- Switches. 2.6 Summary. 2.7 References. 3 Advanced Low Voltage Circuit Techniques. 3.1 Introduction. 3.2 Virtual-Ground Common-Mode Feedback and Output Common-Mode Error Correction. 3.3 Cross-Coupled Passive Sampling Interface. 3.4 Voltage-Controlled Level Shifting. 3.5 Feedback Current Biasing Technique. 3.6 Low-Voltage Finite-Gain-Compensation. 3.7 Low-Voltage Offset-Compensation 3.8 Summary. 3.9 References. 4 Time-Interleaving: Multiplying the Speed of the ADC. 4.1 Introduction. 4.2 Time-Interleaved ADC Architecture. 4.3 Channel Mismatch Analysis. 4.4 Offset Mismatch. 4.5 Gain Mismatch. 4.6 Timing Mismatch. 4.7 Bandwidth Mismatch. 4.8 Summary. 4.9 References. 5 Design of a 1.2V, 10-bit, 60-360MHz Time-Interleaved Pipelined ADC. 5.1 Introduction. 5.2 The Overall ADC Architecture. 5.3 Prototype Circuit-Level Design. 5.4 Layout Considerations. 5.5 Simulation Results. 5.6 Summary. 5.7 References. 6 Experimental Results. 6.1 Introduction. 6.2 The Prototype PCB Design. 6.3 Measurement Setup and Results. 6.4 Summary. 6.5 References. 7 Conclusions and Prospective for Future Work. 7.1 Conclusions. 7.2 Prospective for Future Work. 7.3 References. Appendix 1 Operation Principle of VG-CMFB with O-CMEC. Appendix 2 Mathematical Analysis of Bandwidth Mismatches. Appendix 3 Noise Analysis of Advanced Reset-Opamp Circuits. A3.1 Cross-Coupled Front-End S/H. A3.2 MDAC with Auxiliary Amplifier. Appendix 4 Special Case in Gain mismatch.