Algorithms for Synthesis and Testing of Asynchronous Circuits

The design of asynchronous circuits is increasingly important in solving problems such as complexity management, modularity, power consumption and clock distribution in large digital integrated circuits.
Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by the progressive shift towards synchronous design techniques that had much more structure and were much easier to verify and synthesize. System design requirements made it impossible to totally eliminate the use of asynchronous circuits. Given the objective difficulty encountered by designers, the asynchronous components of electronic systems, such as interfaces, became a serious bottleneck in the design process. The use of new models and some theoretical breakthroughs made it possible to develop asynchronous design techniques that were reliable and effective.
Algorithms for Synthesis and Testing of Asynchronous Circuits describes a variety of mathematical models and of algorithms that form the backbone and the body of a new design methodology for asynchronous design. The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in exploring the possibility of designing asynchronous circuits. It requires a solid mathematical background in discrete event systems and algorithms. While the book has not been written as a textbook, it could nevertheless be used as a reference book in an advanced course in logic synthesis or asynchronous design.
Algorithms for Synthesis and Testing of Asynchronous Circuits also includes an extensive literature review, which summarizes and compares classical papers from the 1960s with the most recent developments in the areas of asynchronous circuit design testing and verification.
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