Advanced Verification Techniques

A Systemc Based Approach for Successful Tapeout

By: Leena Singh, Leonard Drucker

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Hardcover | 8 June 2004

At a Glance

Hardcover
404 Pages

Dimensions(cm)
24.77 x 17.15 x 1.91

Hardcover

$249.00

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"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks."
- Stuart Swan

Industry Reviews

"As chip size and complexity continue to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks."
(Stuart Swan)

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Energy Technology & Engineering Electrical Engineering Computing & I.T.Computer Networking & Communications Graphical & Digital Media Applications Computer-Aided Design CAD

Introduction	p. 1
Verification process	p. 17
Using SCV for verification	p. 45
Functional verification testplan	p. 65
Testbench concepts using SystemC	p. 95
Verification methodology	p. 149
Regression/setup and run	p. 211
Functional coverage	p. 233
Dynamic memory modeling	p. 251
Post synthesis gate simulation	p. 275
Table of Contents provided by Blackwell. All Rights Reserved.

Advanced Verification Techniques

A Systemc Based Approach for Successful Tapeout

At a Glance

Hardcover

Industry Reviews

Shipping

How to return your order

Defective items

You Can Find This Book In

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