PREFACE xix
1 INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES 1
1.1. Semiconductor Memories Overview 1
1.2. Advanced Semiconductor Memory Developments 8
1.3. Future Memory Directions 16
References 18
2 STATIC RANDOM ACCESS MEMORY TECHNOLOGIES 19
2.1. Basic SRAM Architecture and Cell Structures 19
2.1.1. SRAM Performance and Timing Specifications 21
2.1.2. SRAM ReadWrite Operations 23
2.2. SRAM Selection Considerations 26
2.3. High Performance SRAMs 33
2.3.1. Synchronous SRAMs Flow-Through 41
2.3.2. Zero Bus Turnaround SRAMs 43
2.3.3. Quad Data Rate SRAM 44
2.3.4. Double Data Rate SRAM 50
2.3.5. No-Turnaround Random Access Memory 51
2.4. Advanced SRAM Architectures 55
2.5. Low-Voltage SRAMs 61
2.6. BiCMOS Technology SRAMs 75
2.7. SOI SRAMs 79
2.8. Specialty SRAMs 91
2.8.1. Multiport RAMs 92
2.8.1.1. Dual-Port RAMs 92
2.8.1.2. Quadport™ RAMs 101
2.8.2. First-In-First-Out (FIFO) Memories 103
2.8.3. Content Addressable Memories (CAMs) 111
2.8.3.1. Advanced Content Addressable Memories (Examples) 116
References 122
3 HIGH-PERFORMANCE DYNAMIC RANDOM ACCESS MEMORIES 129
3.1. DRAM Technology Evolution and Trends 129
3.2. DRAM Timing Specifications and Operations 133
3.2.1. General Timing Specifications 133
3.2.2. Memory Read Operation 135
3.2.3. Memory Write Operation 138
3.2.4. Read-Modify-Write Operation 140
3.2.5. DRAM Refresh Operation 141
3.3. Extended-Data-Out DRAMS 145
3.3.1. EDO DRAM (Example) 145
3.4. Enhanced DRAM (EDRAM) 146
3.5. Synchronous DRAMGRAM Architectures 150
3.5.1. SDR SDRAMSGRAM 150
3.5.2. DDR SDRAMSGRAM Features 151
3.5.3. Synchronous DRAM 256Mb (Example) 154
3.5.3.1. Initialization 154
3.5.3.2. Register Definition 155
3.5.3.3. Commands 157
3.5.3.4. SDRAM Operations 159
3.6. Enhanced Synchronous DRAM (ESDRAM) 163
3.7. Cache DRAM (CDRAM) 166
3.8. Virtual Channel Memory (VCM) DRAMs 172
3.9. Advaned DRAM Technology Perspectives 175
3.9.1. Memory Capacitor Cell Improvements 179
3.9.2. 64-Mb DRAMs 188
3.9.3. 256-Mb DRAMs 195
3.10. Gigabit DRAM Scaling Issues and Architectures 200
3.11. Multilevel Storage DRAMs 217
3.12. SOI DRAMs 221
References 231
4 APPLICATION-SPECIFIC DRAM ARCHITECTURES AND DESIGNS 237
4.1. Video RAMs (VRAMs) 241
4.2. Synchronous Graphic RAMs (SGRAMs) 244
4.2.1. 64-Mb DDR SGRAM 246
4.2.2. 256-Mb DDR Fast Cycle RAM 253
4.3. Rambus Technology Overview 257
4.3.1. Direct RDRAM Technologies and Architectures 264
4.3.2. Direct Rambus Memory System-Based Designs 272
4.4. Synchronous Link DRAMs (SLDRAMs) 275
4.4.1. SLDRAM Standard 277
4.4.2. SLDRAM Architectural and Functional Overview 283
4.4.3. SLDRAM (Example) 285
4.5. 3-D RAM 296
4.5.1. Pixel ALU Operations 305
4.6. Memory System Design Considerations 309
References 316
5 ADVANCED NONVOLATILE MEMORY DESIGNS AND TECHNOLOGIES 319
5.1. Nonvolatile Memory Advances 319
5.1.1. Introduction 319
5.1.2. Serial EEPROMs 323
5.1.3. Flash Memory Developments 327
5.2. Floating Gate Cell Theory and Operations 334
5.2.1. Floating Gate Cell Theory 334
5.2.2. Charge Transport Mechanisms 339
5.2.2.1. Fowler-Nordheim Tunneling 340
5.2.2.2. Polyoxide Conduction 342
5.2.2.3. Channel Hot-Electron Injection (CHEI) 343
5.2.2.4. Direct Band-to-Band Tunneling 347
5.3. Nonvolatile Memory Cell and Array Designs 350
5.3.1. UV-EPROM (or EPROM) Cells 350
5.3.1.1. T-Cell EPROM 351
5.3.1.2. X-Cell EPROM 351
5.3.1.3. Staggered Virtual Ground (SVG) Cell Array EPROM 352
5.3.1.4. Alternate Metal Virtual Ground (AMG) Cell Array EPROM 353
5.3.2. EEPROM Cells 354
5.3.3. Flash Memory Cells 354
5.3.3.1. T-Cell Flash 355
5.3.3.2. Alternate Metal Ground (AMG) Flash Cell 357
5.3.3.3. Source-Coupled Split-Gate (SCSG) Flash Cell 358
5.3.3.4. Field-Enhancing Tunneling Injector Flash Cell 359
5.3.3.5. Triple-Polysilicon Virtual Ground (TPVG) Flash Cell 362
5.3.3.6. Divided Bit-Line NOR (DINOR) Flash Cell 363
5.3.3.7. AND Flash Cell 365
5.3.3.8. High Capacitive Coupling Ratio (HiCr) Flash Cell 366
5.3.3.9. NAND Flash Cell 366
5.3.4. Flash Memory Cell Basic Operation and Processes 368
5.3.5. Flash EEPROM Technology Developments 372
5.4. Flash Memory Architectures 377
5.4.1. NOR Flash Memories 378
5.4.1.1. AMD NOR Architecture Flash Memories 381
5.4.1.2. Intel Flash Memories 387
5.4.2. NAND Flash Memories 392
5.4.2.1. AMD NAND Architecture Flash Memories 393
5.4.2.2. Samsung 32M x 8-bit NAND Architecture Flash Memory 397
5.4.2.3. Virtual DRAM 401
5.4.3. DINOR Architecture Flash Memories 403
5.4.3.1. A 16-Mb DINOR Flash Memory 405
5.4.3.2. P-Channel DINOR Flash Memory 406
5.4.3.3. BiNOR Cell Flash Memory 408
5.4.4. AND Architecture Flash Memories 410
5.4.5. Specialty Flash Memories 411
5.5. Multilevel Nonvolatile Memories 412
5.5.1. Multilevel NOR Flash Memories 418
5.5.2. Multilevel NAND Flash Memories 426
5.5.2.1. A 512-Mb NAND Flash Memory 429
5.5.3. Multilevel AND Flash Memories 429
5.6. Flash Memory Reliability Issues 430
5.6.1. General Failure Mechanisms for EPROMsEEPROMs 430
5.6.1.1. Stuck Bit 434
5.6.1.2. Data Retention Degradation 434
5.6.1.3. Read Time Degradation 434
5.6.1.4. Erase Time Degradation 434
5.6.1.5. Program Time Degradation 434
5.6.1.6. Disturbs 434
5.6.2. Flash Memory Reliability 435
5.6.2.1. Flash Overerase 436
5.6.2.2. Flash Program Disturbs 436
5.6.2.3. Flash Read Disturbs 437
5.6.2.4. Flash ProgramErase Endurance 437
5.6.2.5. Flash Data Retention Failures 439
5.6.2.6. Flash Hot Carrier Reliability Effects 441
5.6.2.7. Multilevel Flash Reliability 442
5.7. Ferroelectric Memories 443
5.7.1. Technology Overview 443
5.7.2. Ferroelectric Materials and Memory Design 451
5.7.3. Megabit FRAMs 454
5.7.4. Chain FRAM (CFRAM) 463
5.7.5. Metal Ferroelectric Semiconductor FET 465
5.7.6. FRAM Reliability Issues 467
References 469
6 EMBEDDED MEMORIES DESIGNS AND APPLICATIONS 479
6.1. Embedded Memory Developments 479
6.2. Cache Memory Designs 487
6.2.1. Cache Architecture Implementation for a DSP (Example) 495
6.3. Embedded SRAMDRAM Designs 499
6.3.1. Embedded SRAM Macros 503
6.3.1.1. A IT SRAM Macro 504
6.3.1.2. A 4T SRAM Macro 506
6.3.2. Embedded DRAM Macros 508
6.3.2.1. dRAMASICs 508
6.3.2.2. A Compiled 100-MHz DRAM Macro 509
6.3.2.3. A Dual-Port Interleaved DRAM Architecture Macro 511
6.3.2.4. A 1-GHz Synchronous DRAM Macro 513
6.4. Merged Processor DRAM Architectures 516
6.5. DRAM Processes with Embedded Logic Architectures 522
6.5.1. A Modular Embedded DRAM Core 523
6.5.2. Multimedia Accelerator with Embedded DRAM 524
6.5.3. Intelligent RAM (IRAM) 527
6.5.4. Computational RAM 530
6.6. Embedded EEPROM and Flash Memories 533
6.7. Memory Cards and MultiMedia Applications 536
6.7.1. Memory Cards 536
6.7.2. Single-Chip Flash Disk 544
References 547
7 FUTURE MEMORY DIRECTIONS: MEGABYTES TO TERABYTES 549
7.1. Future Memory Developments 549
7.2. Magnetoresistive Random Access Memories (MRAMs) 551
7.2.1. MRAM Technology Developments and Tradeoffs 551
7.2.2. MRAM Cells and Architectures 556
7.2.3. 256K1-Mb GMRAMs 566
7.2.4. Multilevel MRAMs 571
7.3. Resonant Tunneling Diode-Based Memories 572
7.3.1. Resonant Tuneling Diode Theory 572
7.3.2. Tunneling SRAM (TSRAM) Cell Designs 574
7.3.3. RTD-Based Memory System (Example) 579
7.4. Single-Electron Memories 582
7.4.1. Single-Electron Device Theory 582
7.4.2. Single-Electron Memory Characteristics and Configurations 590
7.4.3. Single-Electron Devices Fabrication Techniques 595
7.4.4. Nanocrystal Memory Devices 596
7.5. Phase-Change Nonvolatile Memories 602
7.6. Protonic Nonvolatile Memories 607
7.7. Miscellaneous Memory Technology Development (Examples) 612
7.7.1. Thyristor-Based SRAM Cell (T-RAM) 613
7.7.2. Content Addressable Read-Only Memory (CAROM) 614
7.7.3. Nanotech Memories 618
7.7.4. Solid-State Holographic Memories 618
References 623
INDEX 631
