Test Pattern Generation Using Boolean Proof Engines

By: Rolf Drechsler, Stephan EggersglÃ¼Ã?, GÃ¶rschwin Fey

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Hardcover | 30 April 2009

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208 Pages

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23.5 x 15.88 x 1.91

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In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. The book describes the state of the art in the field, highlights research aspects, and shows directions for future work.

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Preface	p. v
Acknowledgments	p. vii
Introduction	p. 1
Preliminaries	p. 9
Circuits	p. 9
Fault Models	p. 10
Stuck-at Faults	p. 10
Delay Faults	p. 13
Simple ATPG Framework	p. 16
Classical ATPG Algorithms	p. 20
Stuck-at Faults	p. 20
Delay Faults	p. 23
Benchmarking	p. 26
Boolean Satisfiability	p. 29
SAT Solver	p. 29
Advances in SAT	p. 30
Boolean Constraint Propagation	p. 31
Conflict Analysis	p. 32
Variable Selection Strategies	p. 35
Correctness and Unsatisfiable Cores	p. 35
Optimization Techniques	p. 36
Circuit-to-CNF Conversion	p. 38
Circuit-Oriented SAT	p. 41
SAT-Based ATPG	p. 43
Basic Problem Transformation	p. 44
Structural Information	p. 46
Experimental Results	p. 49
Summary	p. 51
Learning Techniques	p. 53
Introductory Example	p. 54
Concepts for Reusing Learned Information	p. 55
Basic Idea	p. 55
Tracking Conflict Clauses	p. 57
Heuristics for ATPG	p. 59
Notation	p. 59
Incremental SAT-Based ATPG	p. 60
Enhanced Circuit-Based Learning	p. 63
Experimental Results	p. 66
Summary	p. 69
Multiple-Valued Logic	p. 71
Four-Valued Logic	p. 71
Industrial Circuits	p. 72
Boolean Encoding	p. 73
Encoding Efficiency	p. 75
Concrete Encoding	p. 77
Multi-input Gates	p. 79
Modeling of Multi-input Gates	p. 79
Bounded Multi-input Gates	p. 82
Clause Generation	p. 83
Experimental Results	p. 84
Four-Valued Logic	p. 84
Multi-input Gates	p. 85
Summary	p. 86
Improved Circuit-to-CNF Conversion	p. 89
Hybrid Logic	p. 90
Incremental Instance Generation	p. 94
Run Time Analysis	p. 94
Incremental Approach	p. 99
Experimental Results	p. 104
Hybrid Logic	p. 105
Incremental Instance Generation	p. 107
Summary	p. 110
Branching Strategies	p. 113
Standard Heuristics of SAT Solvers	p. 113
Decision Strategies	p. 114
Experimental Results	p. 115
Summary	p. 117
Integration into Industrial Flow	p. 119
Industrial Environment	p. 120
Integration of SAT-Based ATPG	p. 123
Test Pattern Compactness	p. 125
Observability at Outputs	p. 125
Applying Local Don't Cares	p. 127
Experimental Results	p. 129
Integration	p. 129
Test Pattern Compactness	p. 132
Summary	p. 135
Delay Faults	p. 137
Transition Delay	p. 138
Path Delay	p. 141
Non-robust Tests	p. 141
Robust Test Generation	p. 143
Industrial Application	p. 145
Structural Classification	p. 149
Encoding Efficiency for Path Delay Faults	p. 151
Compactness of Boolean Representation	p. 153
Efficiency of Compact Encodings	p. 155
Encoding Selection	p. 157
Incremental Approach	p. 158
Experimental Results	p. 161
Transition Delay Faults	p. 161
Encoding Efficiency for Path Delay Faults	p. 163
Robust and Non-robust Tests	p. 166
Incremental Approach	p. 168
Summary	p. 170
Summary and Outlook	p. 173
Bibliography	p. 177
Index	p. 189
Table of Contents provided by Ingram. All Rights Reserved.

Test Pattern Generation Using Boolean Proof Engines

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