Sub-threshold Design for Ultra Low-Power Systems

Cover -- Contents -- 1 Introduction -- 1.1 Energy-Constrained Applications -- 1.1.1 Micro-sensor Networks and Nodes -- 1.1.2 Radio Frequency Identification (RFID) -- 1.1.3 Low-power Digital Signal Processor (DSP) and Microcontroller Units (MCU) -- 1.2 System requirements -- 1.2.1 Battery Lifetimes -- 1.2.2 Energy Harvesting -- 1.3 Book Summary -- 2 Origins of Weak Inversion (or Sub-threshold) Circuit Design -- 3 Survey of Low-voltage Implementations -- 3.1 Technology Scaling -- 3.2 Low-voltage Logic Designs -- 3.3 History of Minimum Voltage -- 3.4 History of Minimum Energy -- 3.5 Survey of Sub-threshold CMOS Circuits -- 4 Minimizing Energy Consumption -- 4.1 Energy-Performance Contours -- 4.1.1 Variable Activity Factor Circuit -- 4.1.2 Energy-Performance Contours -- 4.1.3 Activity Factor -- 4.2 Modeling Minimum Energy Consumption -- 4.2.1 Sub-Threshold Leakage Current Models -- 4.2.2 Other Components of Current -- 4.2.3 Minimum Energy Point Model -- 4.3 Minimum Energy Point Dependencies -- 4.3.1 Operating Scenario -- 4.3.2 Temperature -- 4.3.3 Architecture -- 5 EKV Model of the MOS Transistor -- 5.1 Introduction and Definitions -- 5.2 Density of Mobile Charge -- 5.2.1 Threshold Function -- 5.2.2 Approximation in Strong Inversion -- 5.2.3 General Case -- 5.2.4 Approximation in Weak Inversion -- 5.3 Drain Current and Modes of Operation -- 5.3.1 Charge-Current Relationship -- 5.3.2 Forward and Reverse Components -- 5.3.3 General Current Expression -- 5.3.4 Modes of Operation and Inversion Coefficient -- 5.3.5 Output Characteristics and Saturation Voltage -- 5.3.6 Weak Inversion Approximation -- 5.4 Small-Signal Model -- 5.4.1 Transconductances -- 5.4.2 Residual Conductance in Saturation and Maximum Voltage Gain -- 5.4.3 Small-Signal AC Model -- 5.5 Transistor Operated As a Pseudo-Resistor -- 5.6 Noise -- 5.6.1 Noise model -- 5.6.2 Channel Noise -- 5.6.3 Interface Noise -- 5.6.4 Total Noise -- 5.7 Temperature effects -- 5.8 Non-ideal effects -- 5.8.1 Mismatch -- 5.8.2 Polysilicon Gate Depletion -- 5.8.3 Band Gap Widening -- 5.8.4 Gate Leakage -- 5.8.5 Drain-Induced Barrier Lowering (DIBL) -- 6 Digital Logic -- 6.1 Inverter Operation in Sub-threshold -- 6.1.1 Sub-threshold Inverter Delay -- 6.1.2 Sub-threshold Voltage Transfer Characteristics (VTCs) -- 6.1.3 Inverter Sizing for Minimum Energy -- 6.2 Sub-threshold CMOS Standard Cell Library -- 6.2.1 Parallel Devices -- 6.2.2 Stacked Devices -- 6.2.3 Flip-flops -- 6.2.4 Ratioed Circuits -- 6.2.5 Measured Results from Test Chip -- 6.3 Logic Families in Sub-threshold -- 6.3.1 Process Variation in Sub-threshold Logic -- 6.3.2 Evaluating Logic Styles in the Context of Variations -- 7 Sub-threshold Memories -- 7.1 Register Files -- 7.1.1 Write Port and Memory Cell -- 7.1.