Retargetable Processor System Integration Into Multi-Processor System-On-Chip Platforms

By: Andreas Wieferink, Heinrich Meyr, Rainer Leupers

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Paperback | 15 July 2008

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180 Pages

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23.5 x 15.88 x 1.27

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Foreword. Preface. 1. INTRODUCTION. 1.1 Challenge: From Board to SoC. 1.2 Degrees of SoC Customization. 1.3 Organization of this Book. 2. SOC DESIGN METHODOLOGIES. 2.1 Traditional HW/SW Co-Design. 2.2 System Level Design. 2.3 Current Research on SoC Design Methodologies. 2.4 Contribution of this Work. 3. COMMUNICATION MODELING. 3.1 Transaction Level Modeling. 3.2 Generic Communication Modeling. 3.3 Communication Customization. 3.4 The BusCompiler Tool. 4. PROCESSOR MODELING. 4.1 Generic Processor Modeling. 4.2 Processor Customization Techniques. 4.3 LISA. 5. PROCESSOR SYSTEM INTEGRATION. 5.1 Simulator Structure. 5.2 Adaptors: Bridging Abstraction Gaps. 5.3 Commercial SoC Simulation Environments. 6. SUCCESSIVE TOP-DOWN REFINEMENT FLOW. 6.1 Phase 1: Standalone. 6.2 Phase 2: IA ASIP - AVF Communication Models. 6.3 Phase 3: IA ASIP - CA TLM Bus. 6.4 Phase 4: CA ASIP - CA TLM Bus. 6.5 Phase 5: BCA ASIP - CA TLM Bus. 6.6 Phase 6: RTL ASIP - CA TLM Bus. 6.7 Phase 7: RTL ASIP - RTL Bus. 7. AUTOMATIC RETARGETABILITY. 7.1 MP-SoC Simulator Generation Chain. 7.2 Structure of the Generated Simulator. 7.3 Bus Interface Specification. 8. DEBUGGING AND PROFILING. 8.1 Multiprocessor Debugger. 8.2 TLM Bus Traffic Visualization. 8.3 Bus Interface Analysis. 9. CASE STUDY. 9.1 Multi Processor JPEG Decoding Platform. 9.2 Phase 2: IA+AVF Platform. 9.3 Phase 3: IA + BusCompiler Platform. 9.4 Phase 4: CA + BusCompiler Platform. 9.5 Phase 5: BCA + BusCompiler Platform. 10. SUMMARY. Appendices. A. Businterface Definition Files. A.1 Generic AMBA 2.0 Protocol. A.2 Derived AMBA 2.0 Protocols. A.3 AMBA 2.0 Bus Interface Specification. B. Extended CoWare Tool Flow. List of Figures. References. Index.

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Non-Fiction Computing & I.T.Computer Science Computer Architecture & Logic Design Parallel Processing Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Systems Analysis & Design Artificial Intelligence Expert Systems & Knowledge-Based Systems

Introduction	p. 1
Challenge: From Board to SoC	p. 1
Degrees of SoC Customization	p. 2
Organization of this Book	p. 5
SoC Design Methodologies	p. 7
Traditional HW/SW Co-Design	p. 7
System Level Design	p. 10
Current Research on SoC Design Methodologies	p. 18
Contribution of this Work	p. 22
Communication Modeling	p. 25
Transaction Level Modeling	p. 25
Generic Communication Modeling	p. 29
Communication Customization	p. 32
The BusCompiler Tool	p. 36
Processor Modeling	p. 41
Generic Processor Modeling	p. 41
Processor Customization Techniques	p. 43
LISA	p. 48
Processor System Integration	p. 53
Simulator Structure	p. 53
Adaptors: Bridging Abstraction Gaps	p. 56
Commercial SoC Simulation Environments	p. 63
Successive Top-Down Refinement Flow	p. 67
Phase 1: Standalone	p. 68
Phase 2: IA ASIP [actual symbol not reproducible] AVF Communication Models	p. 72
Phase 3: IA ASIP [actual symbol not reproducible] CA TLM Bus	p. 73
Phase 4: CA ASIP [actual symbol not reproducible] CA TLM Bus	p. 75
Phase 5: BCA ASIP [actual symbol not reproducible] CA TLM Bus	p. 77
Phase 6: RTL ASIP [actual symbol not reproducible] CA TLM Bus	p. 78
Phase 7: RTL ASIP [actual symbol not reproducible] RTL Bus	p. 79
Automatic Retargetability	p. 81
MP-SoC Simulator Generation Chain	p. 81
Structure of the Generated Simulator	p. 83
Bus Interface Specification	p. 85
Debugging and Profiling	p. 91
Multi-Processor Debugger	p. 91
TLM Bus Traffic Visualization	p. 102
Bus Interface Analysis	p. 105
Case Study	p. 109
Multi Processor JPEG Decoding Platform	p. 109
Phase 2: IA + AVF Platform	p. 112
Phase 3: LA + BusCompiler Platform	p. 116
Phase 4: CA + BusCompiler Platform	p. 119
Phase 5: BCA + BusCompiler Platform	p. 122
Summary	p. 127
Businterface Definition Files	p. 131
Extended CoWare Tool Flow	p. 147
List of Figures	p. 149
References	p. 153
Index	p. 161
Table of Contents provided by Blackwell. All Rights Reserved.

Retargetable Processor System Integration Into Multi-Processor System-On-Chip Platforms

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