Reconfigurable Computing: Architectures and Applications : Second International Workshop, ARC 2006, Delft, the Netherlands, March 1-3, 2006 Revised Selected Papers - Koen Bertels

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Reconfigurable Computing: Architectures and Applications

Second International Workshop, ARC 2006, Delft, the Netherlands, March 1-3, 2006 Revised Selected Papers

By: Koen Bertels (Editor), João M.P. Cardoso (Editor), Stamatis Vassiliadis (Editor)

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Paperback | 26 July 2006

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1 The International Workshop on Recon?gurable Computing (ARC) started in 2005 in Algarve, Portugal. The major motivation was to create an event where on-going research e?orts as well as more elaborated, interesting and hi- quality work on applied recon?gurable computing could be presented and d- cussed. Over the last couple of years recon?gurable computing has become a we- known and established research area producing interesting as well as important results in both general and embedded computing systems. It is also getting more and more interest from industry which is attracted by the (design and development) ?exibility as well as the performance improvements that can be expected from this technology. As recon?gurablecomputing has blurred the gap between software and hardware, some even speak of a radical new programming paradigm opening a new realm of unseen applications and opportunities. The logo of the ARC workshop is the Nonius, a measurement instrument used in the Portuguese period of discoveries that was invented by Pedro Nunes, a Portuguesemathematician. As the logo suggests, the main motto of ARC is to help to navigate the world of recon?gurable computing. Driven by this motto, we hope ARC contributes to solid advances on recon?gurable computing.

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You Can Find This Book In

Non-Fiction Computing & I.T.Computer Networking & Communications Computer Hardware Personal Computers Computer Science Computer Architecture & Logic Design Engineering & Technology Electronics & Communications Engineering Electronics Engineering Systems Analysis & Design Network Hardware

Digital Lifestyle & Online World: Consumer & User Guides Portable & Handheld Devices User Guides

Applications
Implementation of Realtime and Highspeed Phase Detector on FPGA	p. 1
Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform	p. 12
Configurable Embedded Core for Controlling Electro-Mechanical Systems	p. 18
Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors	p. 24
Dynamic Partial Reconfigurable FIR Filter Design	p. 30
Event-Driven Simulation Engine for Spiking Neural Networks on a Chip	p. 36
Towards an Optimal Implementation of MLP in FPGA	p. 46
Power
Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture	p. 52
Quality Driven Dynamic Low Power Reconfiguration of Handhelds	p. 59
An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects	p. 65
Image Processing
Highly Paralellized Architecture for Image Motion Estimation	p. 75
Design Exploration of a Video Pre-processor for an FPGA Based SoC	p. 87
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection	p. 93
Applications of Small-Scale Reconfigurability to Graphics Processors	p. 99
An Embedded Multi-camera System for Simultaneous Localization and Mapping	p. 109
Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor	p. 115
Trigonometric Computing Embedded in a Dynamically Reconfigurable Cordic System-on-Chip	p. 122
Handel-C Design Enhancement for FPGA-Based DV Decoder	p. 128
Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the Apaches' Platform	p. 134
A New VLSI Architecture of Lifting-Based DWT	p. 146
Architecture Based on FPGA's for Real-Time Image Processing	p. 152
Real Time Image Processing on a Portable Aid Device for Low Vision Patients	p. 158
General Purpose Real-Time Image Segmentation System	p. 164
Organization and Architecture
Implementation of LPM Address Generators on FPGAs	p. 170
Self Reconfiguring EPIC Soft Core Processors	p. 182
Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs	p. 187
Area/Performance Improvement of NoC Architectures	p. 193
Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array	p. 199
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms	p. 205
Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support	p. 217
A Reconfigurable Data Cache for Adaptive Processors	p. 230
The Emergence of Non-von Neumann Processors	p. 243
Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server	p. 255
A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs	p. 262
A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI	p. 268
PISC: Polymorphic Instruction Set Computers	p. 274
Networks and Communication
Generic Network Interfaces for Plug and Play NoC Based Architecture	p. 287
Providing QoS Guarantees in a NoC by Virtual Channel Reservation	p. 299
Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA	p. 311
A Reconfigurable Architecture for MIMO Square Root Decoder	p. 317
Security
Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking	p. 323
Updates on the Security of FPGAs Against Power Analysis Attacks	p. 335
Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems	p. 347
FPGA Implementation of a GF(2m) Tate Pairing Architecture	p. 358
Iterative Modular Division over GF(2m): Novel Algorithm and Implementations on FPGA	p. 370
Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider	p. 383
Unite: Uniform Hardware-Based Network Intrusion deTection Engine	p. 389
Tools
Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs	p. 401
Automatic Compilation Framework for Bloom Filter Based Intrusion Detection	p. 413
A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware	p. 419
Hardware and a Tool Chain for ADRES	p. 425
Integrating Custom Instruction Specifications into C Development Processes	p. 431
A Compiler-Oriented Architecture Description for Reconfigurable Systems	p. 443
Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility	p. 449
High-Level Synthesis Using Spark and Systolic Array	p. 455
Super Semi-systolic Array-Based Application-Specific PLD Architecture	p. 461
Author Index	p. 467
Table of Contents provided by Ingram. All Rights Reserved.

Reconfigurable Computing: Architectures and Applications

Second International Workshop, ARC 2006, Delft, the Netherlands, March 1-3, 2006 Revised Selected Papers

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