Power-Aware Computer Systems

First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers

By: B. Falsafi (Editor), T.N. Vijaykumar (Editor)

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Paperback | 11 July 2001

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The phenomenal increases in computer system performance in recent years have been accompanied by a commensurate increase in power and energy dissipation. The latter has directly resulted in demand for expensive packaging and cooling technology, an increase in product cost, and a decrease in product reliability in all segments of the computing market. Moreover, the higher power/energy dissipation has signi cantly reduced battery life in portable systems. While - stem designers have traditionally relied on circuit-level techniques to reduce - wer/energy, there is a growing need to address power/energy dissipation at all levels of the computer system. We are pleased to welcome you to the proceedings of the Power-Aware C- puter Systems (PACS 2000) workshop. PACS 2000 was the rst workshop in its series and its aim was to bring together experts from academia and industry to address power-/energy-awareness at all levels of computer systems. In these p- ceedings, we bring you several excellent research contributions spanning a wide spectrum of areas in power-aware systems, from application all the way to c- pilers and microarchitecture, and to power/performance estimating models and tools. We have grouped the contributions into the following speci c categories: (1) power-aware microarchitectural/circuit techniques, (2) application/compiler power optimizations, (3) exploiting opportunity for power optimization in - struction scheduling and cache memories, and (4) power/performance models and tools.

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Power-Aware Microarchitectural/Circuit Techniques System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors	p. 1
Ramp Up/Down Functional Unit to Reduce Step Power	p. 13
An Adaptive Issue Queue for Reduced Power at High Performance	p. 25
Application/Compiler Optimizations
Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform	p. 40
Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering	p. 51
Compiler-Directed Dynamic Frequency and Voltage Scheduling	p. 65
Exploiting IPC/Memory Slack
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power	p. 82
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors	p. 97
Power/Performance Models and Tools
TEM²P²EST: A Thermal Enabled Multi-model Power/Performance ESTimator	p. 112
Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor	p. 126
A Comparison of Two Architectural Power Models	p. 137
Author Index	p. 153
Table of Contents provided by Publisher. All Rights Reserved.

Power-Aware Computer Systems

First International Workshop, PACS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers

At a Glance

Paperback

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