| Introduction | p. 1 |
| Rise of Layout Context Dependence | p. 2 |
| Variability and Uncertainty | p. 3 |
| Characterization vs. Modeling | p. 5 |
| Model to Hardware Matching | p. 6 |
| Design for Manufacturability vs. Statistical Design | p. 6 |
| Sources of Variability | |
| Front End Variability | p. 11 |
| Introduction | p. 11 |
| Variability of Gate Length | p. 15 |
| Gate Length Variability: Overview | p. 15 |
| Contributions of Photolithography | p. 17 |
| Impact of Etch | p. 22 |
| Line Edge Roughness | p. 22 |
| Models of L[subscript gate] Spatial Correlation | p. 24 |
| Gate Width Variability | p. 26 |
| Threshold Voltage Variability | p. 27 |
| Thin Film Thickness | p. 32 |
| Lattice Stress | p. 35 |
| Variability in Emerging Devices | p. 36 |
| Physical Variations Due to Aging and Wearout | p. 39 |
| Summary | p. 40 |
| Back End Variability | p. 43 |
| Introduction | p. 43 |
| Copper Cmp | p. 44 |
| Copper Electroplating | p. 47 |
| Multilevel Copper Interconnect Variation | p. 50 |
| Interconnect Lithography and Etch Variation | p. 52 |
| Dielectric Variation | p. 53 |
| Barrier Metal Deposition | p. 54 |
| Copper and Via Resistivity | p. 55 |
| Copper Line Edge Roughness | p. 56 |
| Carbon Nanotube Interconnects | p. 56 |
| Summary | p. 57 |
| Environmental Variability | p. 59 |
| Introduction | p. 59 |
| Impact of Environmental Variability | p. 60 |
| Analysis of Voltage Variability | p. 65 |
| Power Grid Analysis | p. 66 |
| Estimation of Power Variability | p. 69 |
| Systematic Analysis of Temperature Variability | p. 72 |
| Other Sources of Variability | p. 80 |
| Summary | p. 80 |
| Variability Characterization and Analysis | |
| Test Structures for Variability | p. 83 |
| Test Structures: Classification and Figures of Merit | p. 83 |
| Characterization Using Short Loop Flows | p. 85 |
| Transistor Test Structures | p. 90 |
| Digital Test Structures | p. 93 |
| Summary | p. 96 |
| Statistical Foundations of Data Analysis and Modeling | p. 97 |
| A Brief Probability Primer | p. 98 |
| Empirical Moment Estimation | p. 100 |
| Analysis of Variance and Additive Models | p. 102 |
| Case Studies: Anova for Gate Length Variability | p. 105 |
| Decomposition of Variance Into Spatial Signatures | p. 109 |
| Spatial Statistics: Data Analysis and Modeling | p. 113 |
| Measurements and Data Analysis | p. 113 |
| Modeling of Spatial Variability | p. 116 |
| Summary | p. 119 |
| Design Techniques for Systematic Manufacturability Problems | |
| Lithography Enhancement Techniques | p. 123 |
| Fundamentals of Lithography | p. 124 |
| Process Window Analysis | p. 129 |
| Optical Proximity Correction and Srafs | p. 133 |
| Subresolution Assist Features | p. 136 |
| Phase Shift Masking | p. 138 |
| Non-Conventional Illumination and Impact on Design | p. 144 |
| Nominal and Across Process Window Hot Spot Analysis | p. 145 |
| Timing Analysis Under Systematic Variability | p. 147 |
| Summary | p. 149 |
| Ensuring Interconnect Planarity | p. 151 |
| Overview of Dummy Fill | p. 152 |
| Dummy Fill Concept | p. 155 |
| Algorithms for Metal Fill | p. 155 |
| Dummy Fill for Sti Cmp and Other Processes | p. 159 |
| Summary | p. 159 |
| Statistical Circuit Design | |
| Statistical Circuit Analysis | p. 163 |
| Circuit Parameterization and Simulation | p. 163 |
| Introduction to Circuit Simulation | p. 163 |
| MOSFET Devices and Models | p. 165 |
| MOSFET Device Characterization | p. 167 |
| Statistical Device Characterization | p. 170 |
| Principal Component Analysis | p. 171 |
| Worst-Case Analysis | p. 175 |
| Worst-Case Analysis for Unbounded Parameters | p. 176 |
| Worst-Case Analysis Algorithm | p. 177 |
| Corner-Based Algorithm | p. 179 |
| Worst-Case Analysis Example | p. 179 |
| Statistical Circuit Analysis | p. 185 |
| A Brief SRAM Tutorial | p. 185 |
| Monte Carlo Analysis | p. 187 |
| Response-Surface Analysis | p. 189 |
| Variance Reduction and Stratified Sampling Analysis | p. 192 |
| Summary | p. 195 |
| Statistical Static Timing Analysis | p. 197 |
| Basics of Static Timing Analysis | p. 198 |
| Impact of Variability on Traditional Static Timing Verification | p. 201 |
| Increased Design Conservatism | p. 201 |
| Cost of Full Coverage and Danger of Missing Timing Violations | p. 203 |
| Statistical Timing Evaluation | p. 206 |
| Problem Formulation and Challenges of SSTA | p. 207 |
| Block-Based Timing Algorithms | p. 209 |
| Path-Based Timing Algorithms | p. 217 |
| Parameter Space Techniques | p. 223 |
| Monte Carlo SSTA | p. 226 |
| Statistical Gate Library Characterization | p. 230 |
| Summary | p. 233 |
| Leakage Variability and Joint Parametric Yield | p. 235 |
| Leakage Variability Modeling | p. 235 |
| Joint Power and Timing Parametric Yield Estimation | p. 240 |
| Summary | p. 245 |
| Parametric Yield Optimization | p. 247 |
| Limitations of Traditional Optimization for Yield Improvement | p. 247 |
| Statistical Timing Yield Optimization | p. 254 |
| Statistical Circuit Tuning | p. 254 |
| Linear Programming under Uncertainty | p. 259 |
| Techniques for Timing and Power Yield Improvement | p. 266 |
| Summary | p. 272 |
| Conclusions | p. 273 |
| Appendix: Projecting Variability | p. 275 |
| References | p. 285 |
| Index | p. 303 |
| Table of Contents provided by Ingram. All Rights Reserved. |
