Introduction to Design, Test and Thermal Management of 3D Integrated Circuits xv
Part I Design 1
1 3D DesignStyles 3
Paul D. Franzon
1.1 Introduction 3
1.2 3D-IC Technology Set 3
1.3 Why 3D 6
1.4 Miniaturization 7
1.5 Memory Bandwidth 8
1.6 3D Logic 10
1.7 Heterogeneous Integration 16
1.8 Conclusions 18
References 18
2 Ultrafine Pitch 3D Stacked Integrated Circuits: Technology, Design Enablement, and Application 21
DragomirMilojevic, Prashant Agrawal, Praveen Raghavan, Geert Van der Plas, Francky Catthoor, Liesbet Van der Perre, Dimitrios Velenis, Ravi Varadarajan, and Eric Beyne
2.1 Introduction 21
2.2 Overview of 3D Integration Technologies 23
2.3 Design Enablement of Ultrafine Pitch 3D Integrated Circuits 25
2.4 Implementation of Mobile Wireless Application 32
2.5 Conclusions 38
References 39
3 Power Delivery Network and Integrity in 3D-IC Chips 41
Makoto Nagata
3.1 Introduction 41
3.2 PDN Structure and Integrity 41
3.3 PDN Simulation and Characterization 43
3.4 PDN in 3D Integration 49
References 52
4 Multiphysics Challenges and Solutions for the Design of Heterogeneous 3D Integrated System 53
Alexander Steinhardt, Dimitrios Papaioannou, Andy Heinig, and Peter Schneider
4.1 Introduction 53
4.2 Data Handling for the System View 61
4.3 Electrical Challenges 62
4.4 Mechanical Challenges 67
4.5 Thermal Challenges 68
4.6 Thermomechanical Challenges 72
Acknowledgments 77
References 77
5 Physical Design Flow for 3D/CoWoS®Stacked ICs 81
Yu-Shiang Lin, Sandeep K. Goel, Jonathan Yuan, Tom Chen, and Frank Lee
5.1 Introduction 81
5.2 CoWoS®vs. 3D Design Paradigm 82
5.3 Physical Design Challenges 83
5.4 Physical Design Flow 85
5.5 Physical Design Guideline 94
5.6 TSMC Reference Flows 113
5.7 Conclusion 114
References 114
6 Design and CAD Solutions for Cooling and Power Delivery for Monolithic 3D-ICs 115
Sandeep Samal and Sung K. Lim
6.1 Introduction 115
6.2 New Thermal Issues in Monolithic 3D-ICs 117
6.3 Fast Thermal Analysis with Adaptive Regression 121
6.4 New Power Delivery Issues in Monolithic 3D-ICs 126
6.5 Power Delivery Network Optimization 134
6.5.1 Design Styles 134
6.6 Conclusions 139
References 139
7 Electronic Design Automation for 3D 141
Paul D. Franzon
7.1 Introduction 141
7.2 EDA Flows for 3D-IC 141
7.3 Commercial EDA Support 143
7.4 Modular Partitioning Approaches 143
7.5 Circuit Partitioning 145
7.6 Conclusions 146
References 147
8 3D Stacked DRAM Memories 149
Christian Weis, Matthias Jung, and Norbert Wehn
8.1 3D-DRAM Design Space and DRAM Technology Background 150
8.2 Design Space Exploration of 3D-DRAMs 160
8.3 Architectural 3D Stacked DRAM Controller Optimizations 176
8.4 Conclusion 183
References 184
Part II Test 187
9 Cost Modeling for 2.5D and 3D Stacked ICs 189
Mottaqiallah Taouil, Said Hamdioui, and Erik Jan Marinissen
9.1 Introduction 189
9.2 Testing 3D Stacked ICs 189
9.3 Cost Modeling 191
9.4 3D-COSTAR 193
9.5 Case Studies 196
9.6 Conclusion 207
References 207
10 Interconnect Testing for 2.5D- and 3D-SICs 209
Shi-Yu Huang
10.1 Introduction 209
10.2 Pre-Bond TSV Testing 211
10.3 Post-Bond Interconnect Testing 220
10.4 Concluding Remarks 227
References 228
11 Pre-Bond Testing Through Direct Probing of Large-Array Fine-Pitch Micro-Bumps 231
Erik JanMarinissen, Bart DeWachter, Jorg Kiesewetter, and Ken Smith
11.1 Introduction 231
11.2 Pre-Bond Testing 232
11.3 Micro-Bumps 234
11.4 Probe Technology 236
11.5 Test Vehicle: Vesuvius-2.5D 239
11.6 Experiment Results 242
11.7 Conclusion 249
Acknowledgments 249
References 250
12 3D Design-for-Test Architecture 253
Erik JanMarinissen, Mario Konijnenburg, Jouke Verbree, Chun-Chuan Chi, Sergej Deutsch, Christos Papameletis, Tobias Burgherr, Konstantin Shibin, Brion Keller, Vivek Chickermane, and Sandeep K. Goel
12.1 Introduction 253
12.2 Basic 3D-DfT Architecture 254
12.3 Vesuvius-3D 3D-DfT Demonstrator 257
12.4 Extensions to the Basic 3D-DfT Architecture 265
12.5 Conclusion 276
Acknowledgments 276
References 277
13 Optimization of Test-Access Architectures and Test Scheduling for 3D ICs 281
Sergej Deutsch, Brandon Noia, Krishnendu Chakrabarty, and Erik Jan Marinissen
13.1 Uncertain Parameters in Optimization of 3D Test Architecture and Test Scheduling 282
13.2 Robust Optimization of 3D Test Architecture 285
13.3 Simulation Results 294
13.4 Conclusion 299
References 299
14 IEEE Std P1838: 3D Test Access Standard Under Development 301
Adam Cron, Erik Jan Marinissen, Sandeep K. Goel, TeresaMcLaurin, and Sandeep Bhatia
14.1 Introduction 301
14.2 Overview 303
14.3 Scope and Terminology 304
14.4 Serial Control 306
14.5 Die Wrapper Register 311
14.6 Flexible Parallel Port 317
14.7 Conclusion 322
References 322
15 Test and Debug Strategy for TSMC CoWoS®Stacking Process-Based Heterogeneous 3D-IC: A Silicon Study 325
Sandeep K. Goel, Saman Adham,Min-JerWang, Frank Lee, Vivek Chickermane, Brion Keller, Thomas Valind, and Erik Jan Marinissen
15.1 Introduction 325
15.2 Overview of CoWoS®Stacking Process 327
15.3 CoWoS®Chip Architecture 327
15.4 Test and Diagnosis Architecture 329
15.5 Testing of Passive Silicon Interposer 336
15.6 Experimental and Silicon Results 340
15.7 Conclusion 345
References 345
Part III Thermal Management 347
16 Thermal Isolation and Cooling Technologies for Heterogeneous 3D- and 2.5D-ICs 349
Yang Zhang, Hanju Oh, Yue Zhang, Li Zheng, Gary S.May, and Muhannad S. Bakir
16.1 Thermal Challenges for Heterogeneous 3D-ICs 349
16.2 Thermal Challenges and Solutions for 2.5D-ICs 359
16.3 Electrical and Fluidic Micro-Bumps 363
16.4 High Aspect Ratio TSVs Embedded in A Micro pin Fin Heat Sink 367
16.5 Conclusion 371
References 371
17 Passive and Active Thermal Technologies: Modeling and Evaluation 375
Craig E. Green, Vivek Sahu, Yuanchen Hu, Yogendra K. Joshi, and Andrei G. Fedorov
17.1 Introduction 375
17.2 Integrated Background Heat Sink Approaches 376
17.3 Solid-State Cooling 384
17.4 Passive Cooling: Phase Change Material Regeneration Concerns 393
References 409
18 Thermal Modeling and Model Validation for 3D Stacked ICs 413
Herman Oprins, Federica Maggioni, Vladimir Cherman, Geert Van der Plas, and Eric Beyne
18.1 Introduction 413
18.2 Modeling Methods for the Thermal Analysis of 3D Integrated Structures 413
18.3 3D Stacked Thermal Test Vehicles 421
18.4 Experimental Validation of Thermal Models for 3D-ICs 425
18.5 Inter-die Thermal Resistance 428
References 430
19 On the Thermal Management of 3D-ICs: From Backside to Volumetric Heat Removal 433
Thomas Brunschwiler, Gerd Schlottig, Chin L. Ong, Brian Burg, and Arvind Sridhar
19.1 Introduction: Density Scaling Drives Compute Performance and Efficiency 433
19.2 Thermal Management Landscape for 3D-ICs 434
19.3 Advances on Thermal Interfaces: Percolating Thermal Under fills 437
19.4 Single-Phase Interlayer Cooling: Design Rules toward Extreme 3D 438
19.5 Applicability of Two-Phase Cooling for 3D-ICs 443
19.6 Compact Thermal Modeling Framework 448
19.7 Consequence of Fluid Presence for the Package Topology 449
19.8 Thermal Laminates Enabling Dual-Side Cooling and Electrical Interconnects 453
Interconnects 455
References 456
Index 461
