CMOS Cellular Receiver Front-Ends

CMOS Cellular Receiver Front-Ends: From Specification to Realization deals with the design of the receive path of a highly-integrated CMOS cellular transceiver for the GSM-1800 cellular system. The complete design trajectory is covered, starting from the documents describing the standard down to the systematic development of CMOS receiver ICs that comply to the standard. The design of CMOS receivers is tackled at all abstraction levels: from architecture level, via circuit level, down to the device level, and the other way around. Different receiver architectures are compared with respect to integratability, achievable performance and required building block specifications. The requirements of the GSM-1800 standard are mapped onto a set of measurable specifications for a highly-integrated low-IF receiver and distributed among the different building blocks. Several circuit topologies are presented that realize the main functions of the receive path. The dynamics of the elementary specifications of these circuits are explained in terms of the operating point of the involved devices. Wherever possible, this is done using analytical expressions. Based on these insights, detailed sizing procedures are developed to systematically size these RF circuits for a set of specifications. The feasibility of meeting the requirements of today's high-end cellular standards is demonstrated in a mainstream submicron CMOS technology by the development of two highly-integrated GSM-1800 receivers. The theoretical core of the book discusses the fundamental and more advanced aspects of RF CMOS design. It focuses specifically on all aspects of the design of high-performance CMOS low-noise amplifiers. Attempts are made to reconcile the analog designer's and the RF designer's point of view on how to look at submicron CMOS transistors. Special attention is given to the fallacies and pitfalls of input matching in a CMOS context. A methodology for the systematic design of CMOS low-noise amplifiers is presented which is based on a bank of analytical equations for all important LNA specifications. The method is validated by the design of a low power, extremely low noise CMOS GPS LNA.