Wafer-Level Integrated Systems

1. Introduction and Overview.- 1.1 Device vs System Scaling.- 1.2 Major Implementation Issues.- 1.2.1 Reconfiguration Mechanisms.- 1.2.2 Architecural Reconfiguration Issues.- 1.2.3 Defects vs Failures.- 1.2.4 Yield Models.- 1.2.5 Fault Modeling.- 1.2.6 Testing.- 1.2.7 Reconfiguration Algorithms.- 1.2.8 WSI Packaging.- 1.3 ESPRIT 824 WSI Program.- References.- 2. Interconnect Issues.- 2.1 Physical Interconnect Hierarchy.- 2.2 Recursive vs Non-Recursive Interconnect Links.- 2.3 On-Chip Interconnect Lengths.- 2.4 Inter-Chip Connection Lengths.- 2.5 Electrical Models of Interconnection Lines.- 2.6 Minimum Line Capacitance.- 2.7 Scaling of On-Chip Interconnections.- 2.8 Chip-to-Board Interconnect Discontinuity.- 2.9 Comparison of Packaging Schemes.- 2.10 Clock Distribution and Clock Skew.- References.- 3. Fabrication Defects.- 3.1 Substrate defects.- 3.1.1 The "perfect" crystal and Intrinsic Defects.- 3.1.2 Crystal growth and defects.- 3.1.3 Dislocations and stacking faults.- 3.1.4 Gettering for low defect density active regions.- 3.1.5 Wafer flatness distortions.- 3.2 Lithography-induced defects.- 3.2.1 Photoresists-induced defects.- 3.2.2 Resist pattern exposure.- 3.2.3 Mask-to-mask alignment errors.- 3.3 Thin Film Defects.- 3.3.1 Metal line defects.- 3.3.2 Dielectric defects.- 3.3.3 Interlayer vias/contacts.- References.- 4. Reliability and Failures.- 4.1 Failure rate modeling.- 4.1.1 Failure Rate Measures.- 4.1.2 Analytic models.- 4.2 General reliability of IC's.- 4.2.1 Bathtub reliability rate curve.- 4.2.2 Models for thermally activated failures.- 4.2.3 Oxide breakdown.- 4.2.4 Oxide wearout.- 4.2.5 Hot electron injection induced failure.- 4.3 Failure due to metal electromigration.- 4.4 Failure rates under MOS dimensional and voltage scaling laws.- References.- 5. Yield models and Analysis.- 5.1 General yield models.- 5.2 Early yield models.- 5.3 General IC yield models.- 5.4 VLSI yield models based on yield observations.- 5.5 Defect size distributions and critical areas.- 5.6 Yield simultion in VLSI CAD tools.- 5.7 Appendix.- References.- 6. Fault Modeling.- 6.1 General fault modeling issues.- 6.2 Definitions.- 6.3 Stuck-at faults and weak 0/1 faults.- 6.4 "Stuck" transistor faults.- 6.5 Bridging faults.- 6.6 Metastability in latches and flip-flops.- References.- 7. General testing techniques.- 7.1 General Test issues.- 7.1.1 Manufacturing defect testing.- 7.1.2 In-service testing.- 7.1.3 General purpose vs special purpose testing.- 7.2 Scan path test design.- 7.3 LSSD-based Test Methodologies.- 7.4 Pseudorandom test pattern generators.- 7.5 Test response compression.- 7.5.1 General test response analysis schemes.- 7.5.2 Counting response analysis.- 7.5.3 Signature analysis.- 7.5.4 Parallel data signature analysis.- References.- 8. Function-Specific Testing.- 8.1 Memory testing.- 8.1.1 General memory organization.- 8.1.2 Functions requiring fault models.- 8.1.3 Memory cell array fault models.- 8.1.4 Decoder logic fault models.- 8.1.5 Read/write logic fault models.- 8.1.6 Memory test algorithms.- 8.2 Built-in testing of regular arrays.- 8.2.1 Testing linear iterative arrays.- 8.2.2 C-testable array multipliers.- 8.2.3 Recomputing with shifted operands.- 8.2.4 Algorithm-based fault tolerance.- 8.3 Testable programmable logic arrays.- 8.3.1 Physical and logical fault models.- 8.3.2 Design for testable PLA's.- References.- 9. Physical Restructuring.- 9.1 General Restructuring Techniques.- 9.2 Laser "zapping" for memory repair.- 9.3 Electronically field-programmable anti-fuses.- 9.4 Laser-assisted chemical processing.- 9.4.1 General laser-enhanced chemical processing.- 9.4.2 General applications.- 9.4.3 Laser-assisted chemical processing for interconnect restructuring.- 9.5 Focussed ion beams for restructuring.- 9.6 Electron beam restructuring.- 9.7 Restructurable VLSI program.- 9.7.1 Laser vertical links.- 9.7.2 Laser diffused link.- 9.7.3 Software tools for RVLSI.- References.- 10. Programmable Electronic Reconfiguration Switches.- 10.1 General switching issues.- 10.1.1 Area overhead.- 10.1.2 General delay issues.- 10.1.3 Comparison of physical and electronic reconfiguration.- 10.2 Reconfigurable processors.- 10.3 WASP (The WAfer-scale Systolic Processor).- 10.4 Representative switch configurations.- 10.5 Non-lattice reconfiguration switch organizations.- References.- 11. Formal Models of Reconfiguration.- 11.1 Introduction.- 11.2 Probabilistic bounds: Linear arrays.- 11.2.1 General results on fault distributions.- 11.2.2 Patching method.- 11.2.3 The minimum spanning tree method of Leighton and Leiserson.- 11.2.4 The minimum spanning tree method of Greene and Gamal.- 11.3 Probabilistic bounds: 2-dimensional arrays.- 11.3.1 Tree-of-meshes algorithm.- 11.3.2 Divide and conquer method.- 11.4 The Diogenes approach of Rosenberg.- 11.5 Self-reconfiguration algorithms.- 11.6 Spare roow/column allocation algorithms.- References.- 12. Silicon Wafer Hybrids.- 12.1 Introduction.- 12.2 Wafer transmission module.- 12.2.1 WTM technology.- 12.2.2 3-D wafer-stacks.- 12.2.3 Performance issues.- 12.3 AVP modules.- 12.4 Programmable hybrid wafer circuits.- 12.5 MicroChannel cooling and chip attachment.- 12.6 Microwave performance issues.- 12.7 Chip Templates.- 12.8 Other Silicon Circuit Board Studies.- 12.8.1 Self-Aligned Solder Bump Chip Attachment.- 12.8.2 Stacked Wafer Modules.- References.- 13. Optical Interconnections.- 13.1 optical interconnects.- 13.1.1 Electronic On-Chip Data Rates.- 13.1.2 Electronic Interconnection Energy Burdens.- 13.1.3 Energy Burden of Optical Links.- 13.1.4 Energy Burden of Wafer-to-Wafer Interconnections.- 13.2 Optical Interconnect Components.- 13.2.1 Optical Transmission Medium.- 13.2.2 Optical "Connectors".- 13.2.3 Optical Sources and Detectors.- References.