The current trend towards the realization of complex and versatile Systems on a Chip requires the combined efforts and attention of experts in a wide range of areas including microsystems, embedded hardware/software systems, dedicated ASIC and programmable logic hardware, reconfigurable computing, wireless communications and RF issues, video and image processing, memory systems, low power design techniques, design, test and verification algorithms, modeling and simulation, logic synthesis, and interconnect analysis. Thus, the contributions presented herein address a wide range of Systems on a Chip problems. VLSI: Systems on a Chip comprises the selected proceedings of the Tenth International Conference on Very Large Scale Integration (VLSI '99), which was sponsored by the International Federation for Information Processing (IFIP) and was held in Lisbon, Portugal, in December 1999. The volume is organized around two themes, in which the following topics are addressed: VLSI Systems Design and Applications Analog Systems Design Analog Modeling and Design Image Processing Reconfigurable Computing Memory and System Design Low Power Design VLSI Design Methods and CAD Test and Verification Analog CAD and Interconnect Fundamental CAD Algorithms Verification and Simulation CAD for Physical Design High-Level Synthesis and Verification of Embedded Systems VLSI: Systems on a Chip is essential reading for researchers working on system integration, design, and CAD.
Preface. Conference Committees. Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application; S. Li, et al. An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices; G.B. Jackson, et al. A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process; B. Li, H. Tenhunen. A Lower Power CMOS Micromixer for GHz Wireless Applications; Y. Wu, et al. High Current, Low Voltage Current Mirrors and Applications; S.S. Rajput, S.S. Jamuar. Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications; Y. Wu, et al. A Fast Parametric Model for Contact-Substrate Coupling; N. Masoumi, et al. A Feature Associative Processor for Image Recognition Based on A-D merged Architecture; A. Iwata, et al. Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications; A.M. Rassau, et al. Implementation of a Wavelet Transform Architecture for Image Processing; C. Diou, et al. Scalable Run Time Reconfigurable Architecture; A. Touhafi, et al. Frontier: A Fast Placement System for FPGAs; R. Tessier. Dynamically Reconfigurable Implementation of Control Circuits; N. Lau, V. Sklyarov. An IEEE Compliant Floating Point MAF; R.V.K. Pillai, et al. Design and Analysis of On-Chip CPU Pipelined Caches; C. Ninos, et al. Synchronous to Asynchronous Conversion - A Case Study: the Blowfish Algorithm Implementation; J.M.S. Alcantara, et al. Clock Distribution Strategy for IP-based Development; R.L. Aguiar, et al. An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures; D.H. Albonesi. Single Ended Pass-Transistor Logic -- A Comparison with CMOS and CPL; M. Munteanu, et al. Multithreshold Voltage Technology for Low Power Bus Architecture; A. Rjoub, O. Koufopavlou. Integrating Dynamic Power Management in the Design Flow; A. Mota, et al. Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI; S. Lachowicz, et al. On Defect-Level Estimation and the Clustering Effect; J.T. de Sousa. FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC Circuits; J.S. Augusto, C.F.B. Almeida. Design Error Diagnosis in Digital Circuits without Error Model; R. Ubar, D. Borrione. Efficient RLC Macromodels for Digital IC Interconnect; B. Tutuianu, et al. A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications; A. Doboli, R. Vemuri. A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements; A. Nunez-Aldana, R. Vemuri. RF Interface Design Using Mixed-Mode Methodology; A. Gallegos, et al. History-Based Dynamic Minimization During BDD Construction; R. Drechsler, W. Gunther. Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems; L.P. Carloni, et al. Satisfiability-Based Functional Delay Fault Testing; J. Kim, et al. Verification of Abstracted Instruction Cache of TITAC2: A Case Study; T. Yoneda. Speeding Up Look-up-Table Driven Logic Simulation; R. Murgai, et al. Efficient Verification of Behavioral Models Using Sequential Sampling Technique; T. Chen, et al. Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies; S. Raimbault, et al. A Virtual CMOS Library Approach for East Layout Synthesis; F. Moraes, et al. RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime; A. Durbha, S. Katkoori. Designing a Mask Programmable Matrix for Sequential Circuits; F. Lima, et al. Placements Benchmarks for 3-D VLSI; S.T. Obenaus, T.H. Szymanski. Substrate Noise: Analysis, Models, and Optimization; E. Charbon, J. Phillips. Architectural Transformations for Hierarchical Algorithmic Descriptions; M.Y. Teruya, et al. An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs; J.M.P. Cardoso, H.C. Neto. Object-Oriented Modeling and Co-Simulation of Embedded Systems; F.R. Wagner, et al. Architectural Synthesis with Interconnection Cost Control; C. Jego, et al. CAE Environment for Electromechanical Microsystems; R. Lerch, et al. Cost Consideration for Application Specific Microsystems Physical Design Stages -- A New Approach for Microtechnological Process Design; R. Bruck, et al. Moving MEMS into Mainstream Applications: The MEMSCAP Solution; K. Liateni, et al. Trends in RF Simulation Algorithms; J. Phillips, D. Feng. Device Modeling and Measurement for RF Systems; F. Sischka. Reconfigurable Computing: Viable Applications and Trends; A.M.S. Adario, S. Bampi. Hardware Synthesis from Term Rewriting Systems; J.C. Hoe, Arvind. A Synthesis Algorithm for Modular Design of Pipelined Circuits; M.-C. Marinescu, M. Rinard. A Methodology and Associated CAD Tools for Support of Concurrent Design of MEMS; B.F. Romanowicz, et al. SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters?; M.G. Walker, et al. ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect; A. Kirschbaum, et al. Index.
Series: International Federation for Information Processing
Number Of Pages: 678
Published: December 2009
Publisher: SPRINGER VERLAG GMBH
Country of Publication: NL
Dimensions (cm): 23.39 x 15.6
Weight (kg): 1.14