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VHDL Modeling for Digital Design Synthesis - Yu-Chin Hsu

VHDL Modeling for Digital Design Synthesis

Hardcover Published: 31st July 1995
ISBN: 9780792395973
Number Of Pages: 356

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VHDL is a hardware description language that allows the specification of a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. Originally introduced as a hardware description language that permitted the simulation of digital designs, VHDL is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this is that not all of its constructs are useful in synthesis. VHDL has data structures, such as files and pointers, which are useful for simulation but not for actual synthesis. As a result, synthesis tools accept only subsets of VHDL. VHDL Modeling for Digital Design Synthesis covers the synthesis aspects of VHDL, keeping the simulation specifics to a minimum. Audience: Working professionals as well as graduate or undergraduate students who can use the book to get acquainted with VHDL and to learn how it can be used in modeling or digital design.

List of figures
Preface
Introduction
Basic structures in VHDL
Types, operators and expressions
Sequential statements
Concurrent statements
Subprograms and packages
Modeling at the structural level
Modeling at the RT level
Modeling at the FSMD level
Modeling at the algorithmic level
Memories
VHDL synthesis
Writing efficient VHDL descriptions
Practicing designs
References
A
B
Index
Table of Contents provided by Publisher. All Rights Reserved.

ISBN: 9780792395973
ISBN-10: 0792395972
Audience: General
Format: Hardcover
Language: English
Number Of Pages: 356
Published: 31st July 1995
Publisher: Springer
Country of Publication: US
Dimensions (cm): 24.64 x 16.2  x 2.82
Weight (kg): 0.74

Earn 648 Qantas Points
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