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VHDL Coding Styles and Methodologies - Ben Cohen

VHDL Coding Styles and Methodologies

By: Ben Cohen

Book with Other Items

Published: January 1999
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VHDL Coding Styles and Methodologies, Second Edition is a follow-up book to the first edition of the same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy-to-read book that gave in-depth coverage of both the language and coding methodologies. This new edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD, which also includes the GNU toolsite with EMACS language-sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology graciously included an evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity is kindly making available an evaluation version of Synplify, a very efficient, user-friendly and easy-to-use FPGA synthesis tool. Synplify provides a user with both the RTL and gate-level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool. VHDL Coding Styles and Methodologies, Second Edition is intended for professional engineers as well as students. It is organized in thirteen chapters, each covering a separate aspect of the language, with complete examples. It provides a practical approach to learning VHDL. Combining methodologies and coding styles, along with VHDL rules, leads the reader in the right direction from the beginning. CD INCLUDED VHDL Coding Styles and Methodologies, Second Edition includes a CD that contains All code included in the book GNU EMACS language-sensitive editor with VHDL, Verilog, and templates for other languages GNU TSHELL tools that emulate Unix shell Thirty-day evaluation of ModelSim VHDL compiler/simulator from Model Technology Twenty-day evaluation of Synplify VHDL/Verilog FPGA synthesizer from Synplicity VHDL template demonstrating the language syntax VHDL '87 and VHDL '93 formal syntax in HTML format .

Preface
VHDL Overview and Concepts
Basic Language Elements
Control Structures
Drivers
VHDL Timing
Elements of Entity/Architecture
Subprograms
Packages
User Defined Attributes, Specifications, and Configurations
Design for Synthesis
Functional Models and Testbenches
UART Project
VHDL 93 and VHDL 87 Syntax Summary
Package Standard
Package Textio
STD_Logic_Textio
Package STD_Logic_1164
Numeric_STD
STD_Logic_Unsigned
STD_Logic_Signed
STD_Logic_Arith
STD_Logic_Misc
VHDL Predefined Attributes
Index
Table of Contents provided by Publisher. All Rights Reserved.

ISBN: 9780792384748
ISBN-10: 0792384741
Audience: Professional
Format: Book with Other Items
Language: English
Number Of Pages: 455
Published: January 1999
Publisher: Springer
Country of Publication: NL
Dimensions (cm): 26.06 x 18.19  x 3.02
Weight (kg): 0.98
Edition Number: 2
Edition Type: Revised