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Verification by Error Modeling : Using Testing Techniques in Hardware Verification - Katarzyna Radecka

Verification by Error Modeling

Using Testing Techniques in Hardware Verification

Hardcover Published: 30th November 2003
ISBN: 9781402076527
Number Of Pages: 216

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This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.

From the reviews:

"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. ... The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)

List of Figuresp. xi
Acknowledgmentsp. xv
Introductionp. 1
Design Flowp. 1
Verification--Approaches and Problemsp. 4
Verification Approachesp. 5
Verification by Simulationsp. 5
Test Vector Generationp. 5
Design Error Modelsp. 7
Other Simulation Methodsp. 9
Coverage Verificationp. 9
Other Metricsp. 10
Formal Verificationp. 11
Model-based Formal Verification Methodsp. 12
Proof-theoretical Formal Verification Methodsp. 14
Spectral Methods in Verificationp. 14
Book Objectivesp. 15
Boolean Function Representationsp. 19
Background--Function Representationsp. 19
Truth Tablesp. 20
Boolean Equations--Sum of Productsp. 21
Satisfiability of Boolean Functionsp. 23
Algorithms for Solving Satisfiabilityp. 24
Shannon Expansionp. 28
Polynomial Representationp. 28
Decision Diagramsp. 30
Reduced Ordered Binary Decision Diagramsp. 31
Word-Level Decision Diagramsp. 33
Binary Moment Diagramsp. 33
Limitations of WLDDsp. 35
Spectral Representationsp. 38
Walsh-Hadamard Transformp. 39
Walsh Transform Variationsp. 40
Walsh-Hadamard Transform as Fourier Transformp. 41
Arithmetic Transformp. 44
Calculation of Arithmetic Transformp. 47
Fast Arithmetic Transformp. 47
Boolean Lattice and AT Calculationp. 48
AT and Word-Level Decision Diagramsp. 49
Don't Cares and Their Calculationp. 51
Incompletely Specified Boolean Functionsp. 51
Don't Cares in Logic Synthesisp. 51
Don't Cares in Testing for Manufacturing Faultsp. 52
Don't Cares in Circuit Verificationp. 54
Using Don't Cares for Redundancy Identificationp. 55
Basic Definitionsp. 56
Calculation of All Don't Care Conditionsp. 57
Computation of Controllability Don't Caresp. 57
Algorithms for Determining CDCsp. 59
Algorithms for Computing ODCsp. 65
Approximations to Observability Don't Cares--CODCsp. 67
Testingp. 71
Introductionp. 71
Fault List Reductionp. 73
Overview of Simulatorsp. 73
True-Value Simulator Typesp. 74
Logic Simulatorsp. 75
Fault Simulatorsp. 79
Random Simulationsp. 81
Linear Feedback Shift Registersp. 82
Other Pseudo-Random Test Pattern Generatorsp. 88
Final remarksp. 93
Deterministic Vector Generation--ATPGp. 94
Deterministic Phasep. 94
Search for Vectorsp. 98
Fault Diagnosisp. 100
Conclusionsp. 101
Design Error Modelsp. 103
Introductionp. 103
Design Errorsp. 105
Explicit Design Error Modelsp. 107
Detecting Explicit Errorsp. 110
Application of Stuck-at-value Vector Setp. 110
Detection of Gate Replacementsp. 110
Universal Test Set Approachp. 111
Implicit Error Model Precursorsp. 112
Rationale for Implicit Modelsp. 113
Related Work--Error Modelsp. 114
Port Fault Modelsp. 114
Additive Implicit Error Modelp. 115
Arithmetic Transform of Basic Design Errorsp. 117
Design Error Detection and Correctionp. 123
Path Trace Procedurep. 125
Back-propagationp. 126
Boolean Difference Approximation by Simulationsp. 127
Conclusionsp. 128
Design Verification by ATp. 129
Introductionp. 129
Detecting Small AT Errorsp. 132
Universal Test Setp. 132
AT-based Universal Diagnosis Setp. 133
Bounding Error by Walsh Transformp. 135
Spectrum Comparisonp. 137
Spectrum Distribution and Partial Spectra Comparisonp. 138
Absolute Value Comparisonp. 140
Experimental Resultsp. 142
Improvements--Neighborhood Subspace Pointsp. 145
Conclusionsp. 146
Identifying redundant gate and wire replacementsp. 147
Introductionp. 147
Gate Replacement Faultsp. 149
Redundant Replacement Faultsp. 150
Overview of the Proposed Approachp. 151
Redundancy Detection by Don't Caresp. 151
Using Local Don't Caresp. 152
Using Testing--Single Minterm Approximationp. 154
Redundant Single Cube Replacementsp. 159
Use of SAT in Redundancy Identificationp. 160
Passing Proximity Information to SATp. 161
Exact Redundant Fault Identificationp. 163
Preprocessingp. 164
Identifying Redundant Wire Replacementsp. 164
Wire Replacement Faults and Rewiringp. 166
Detection by Don't Caresp. 167
Don't Care Approximationsp. 169
SAT for Redundant Wire Identificationp. 170
Approximate Redundancy Identificationp. 171
Exact Wire Redundancy IDentificationp. 172
I/O Port Replacement Detectionp. 175
Detection of I/O Port Wire Switching Errorsp. 175
Experimental Resultsp. 177
Gate Replacement Experimentsp. 177
Minimum Distance Replacementsp. 177
Wire Replacement Experimentsp. 182
True Fan-in Acyclic Replacementsp. 184
SAT vs. ATPGp. 185
Conclusionsp. 185
Conclusions and future workp. 187
Conclusionsp. 187
Future Workp. 189
Appendicesp. 191
Referencesp. 197
Indexp. 211
Table of Contents provided by Ingram. All Rights Reserved.

ISBN: 9781402076527
ISBN-10: 1402076525
Series: Frontiers in Electronic Testing
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 216
Published: 30th November 2003
Publisher: Springer-Verlag New York Inc.
Country of Publication: US
Dimensions (cm): 23.5 x 15.5  x 1.27
Weight (kg): 1.12