The tremendous growth in wireless and mobile communications has placed stringent requirements on channel spacing and, by implication, on the phase noise of oscillators. Compounding the challenge has been a recent drive toward implementations of transceivers in CMOS, whose inferior l/f noise performance has usually been thought to disqualify it from use in all but the lowest-performance oscillators. Low noise oscillators are also highly desired in the digital world. The continued drive toward higher clock frequencies translates into a demand for ever-decreasing jitter. There is a need for a deep understanding of the fundamental mechanisms governing the process by which device, substrate, and supply noise turn into jitter and phase noise. Existing models generally offer only qualitative insights, however, and it has not always been clear why they are not quantitatively correct. The Design of Low Noise Oscillators offers a new time-variant phase noise model. By discarding the implicit assumption of time- invariance underlying many other approaches, this model is capable of making quantitative predictions of the phase noise and jitter of different types of oscillators. It is able to attribute a definite amount of phase noise to every noise source in the circuit. Because of its time-variant nature, the model also takes into account the effect of cyclostationary noise sources in a natural way. It details the precise mechanism by which low frequency noise, such as l/f noise, upconverts into close-in phase noise. An important new understanding is that rise and fall time symmetry controls such upconversion. More important, it suggests practical methods for suppressing this upconversion, so that good oscillators can be built in technologies with notoriously poor l/f noise performance (such as CMOS or GaAs MESFET). The Design of Low Noise Oscillators will be of interest to both analog and digital circuit as well as RF circuit designers.