System on Chip Design Languages

Contributors. Preface. HDL standardization. 1. HDLCon'01. VHDL-2001: What's new; P.J.Menchini, J. Bhasker 2. HDLCon'01. Verilog-2001. Behavioral and Synthesis Enhancements; C.E. Cummings. 3. HDLCon'01. Advanced ASIC Sign-off Features of IEEE 1076.4-2000 and Standards Updates to Verilog and SDF; S. Wadsworth, D. Brophy. Analog System Modeling And Design. 4. FDL'01. VHDL-AMS model of a synchronous oscillator including phase noise; A. Fakhfakh, N. Milet-Lewis, J-B. Begueret, H. Levi. 5. FDL'01. AnalogSL: A C++ Library for Modeling analog power drivers; Ch. Grimm, P.Oehler, Ch. Meise, K. Waldschmidt, W. Frey. 6. FDL'01. Modeling micro-mechanical structures for system simulations; L.M. Vosskamper, R. Schmid, G. Pelz. 7. HDLCon'01. A Comparison of Mixed-Signal Modeling Approaches; G.D. Peterson. 8. FDL'01. A unified IP Design Platform for extremely flexible High Performance RF and AMS Macros using Standard Design Tools; R. Wittmann, D. Bierbaum, P. Ruhanen, W. Schardein, M. Darianian. 9. FDL'01. Analogue Filter Synthesis from VHDL-AMS; F.A. Hamid, T.J. Kazmierski. System Design Experiences. 10. Con'01. Using GNU Make to Automate the Recompile of VHDL SoC Designs; M.D. McKinney. 11. HDLCon'01. Wild Blue Yonder: Experiences in Designing an FPGA with State Machines for a Modern Fighter Jet, Using VHDL and Design Book; B.L. Snyder. 12. FDL'01. Analysis of Modeling and Simulation Capabilities in SystemC and Ocapi using a Video Filter Design; B. Thornberg, M. O'Nils. 13. FDL'01. The Guidelines and JPEG Encoder Study Case of System-Level Architecture Exploration Using the SpecC Methodology; L. Cai, M. Olivarez, D. Gajski. 14. FDL'01. Provision and Integration of EDA Web-Services using WSDL-based Markup; H-J Eikerling, W. Thronicke, S. Bublitz. System Verification. 15. HDLCon'01. A Mixed C/Verilog Dual-Platform Simulator; D.A. Burgoon, E.W. Powell, J.A. Sundragon Waitz. 16. HDLCon'01. Assertions Targeting a Diverse Set of Verification Tools; H.D. Foster, C.N. Coelho, Jr. 17. HDLCon'00. Predicting the Performance of SoC Verification Techniques; G. D. Peterson. System Specification. 18. FDL'01. Aspects of object-oriented hardware modeling with SystemC-Plus; E. Grimpe, F. Oppenheimer. 19. FDL'01. UML for system-level design; P. Green, M. Edwards, S. Essa. 20. FDL'01. Open PROMOL: An Experimental Language for Target Program Modification; V. Dtuikys, R. Damaoevieius, G. Ziberkas. 21. FDL'01. A system benchmark specification experiment with Esterel/C; L. Ribas, J. Saiz, J. Carrabina. Real-Time Modeling. 22. FDL'01. Modeling of real-time embedded systems by using SDL; A. Alkhodre, J-H. Babau, J-J. Schwarz. 23. FDL'01. A framework for specification and verification of timing constraints; E. Villar. 24. FDL'01. A general approach to modeling system-level timing constraints; M. Jersak, D. Ziegenbein, R. Ernst.